Rochester Electronics’ Original Engineering-Driven Test Protocol Assures Accurate, Comprehensive Testing of All Manufactured Semiconductor Devices

Rochester Electronics ensures that the proper test techniques and methodologies required for all flow classifications and component types are always met. Rochester’s Original Engineering–Driven Test Protocol offers a unique advantage in providing high-quality, high-performance, and thoroughly tested replacements for end-of-life and mature semiconductor devices.

As the world’s largest authorized manufacturer and distributor of end-of-life and mature semiconductors, in most cases, Rochester acquires intellectual property from the original semiconductor manufacturer through continuing manufacturing agreements, including proprietary testing techniques, test programs, tooling, and test equipment required for precise and comprehensive testing of the semiconductor devices. To guarantee the most accurate testing available, Rochester continuously updates its test equipment and installs the same model machines used by the original manufacturer. In applying Rochester’s Original Engineering-Driven Test Protocol, Rochester engineers use the manufacturer’s factory-approved test programs or, when appropriate, upgrade those programs or even develop new test programs. The ultimate goal is always to perform the most comprehensive testing.

When the original test programs and/or test systems are unavailable from the original manufacturer, Rochester’s dedicated test engineers develop new test programs based on the latest revisions of the data sheets. Because the test process is relied upon to prevent defective components being shipping to customers as “good” devices, it is critical to correctly match the proper test techniques with the overall component/system requirements. Rochester’s test engineers have extensive experience with fault conditions and fault classes that can exist exclusively to certain technologies (for example, IDDQ testing of CMOS devices) and product classifications (for example, blown fuse faults in PLDs). This knowledge facilitates the implementation of the appropriate test techniques and methodologies that produce accurate results. If necessary, Rochester engineers convert test programs to existing test platforms using proven in-house custom conversion software tools.

“The Original Engineering–Driven Test Protocol combines our strategic partnership agreements with our advanced engineering approach to provide high-quality testing and highly reliable semiconductor devices,” said Gary G. Francoeur, director of engineering and test operations at Rochester Electronics. “The proper test strategy for any product must balance the overall cost of test with the required quality and reliability level for the end-use of the component. Cost of test strategies from independent and third-party test labs are frequently dictated by competition and the demand for quick turnaround times; and cost-cutting shortcuts can negatively impact the quality of the test process.”

Rochester matches components to test techniques using advanced methods and processes developed in its 30,000-square-foot testing lab, which features a DSCC burn-in lab suitable for method 1015 and method 1005 testing. Rochester engineers routinely perform static and dynamic burn-in and hot and cold wafer probing. Rochester can sort wafers in house up to eight inches (200mm) in diameter using either Electroglas or TEL probers. In addition, Rochester is certified for V-level (space) products and can manufacture and test many products to JAN-S, V-level, or to customer space-level requirements.

“Although semiconductor manufacturing quality levels have been generally improving over the past two decades, the industry’s aggregate evolution reinforces the necessity to completely and accurately test semiconductor devices,” said Paul Gerrish, co-president at Rochester Electronics. “In fact, as semiconductors are becoming more complex, expanding in density and shrinking topologies, comprehensive testing requirements are, in effect, escalating in order to abate residual defect rates. Higher device speeds and pin count, surface mount packaging, and board interconnect technologies are also having adverse effects on device testability.”