Agilent Introduces Enhanced Solution For PCI Express 3.0 Receiver Characterization

Using the Agilent test set, design and test engineers in the semiconductor and computer industry can accurately characterize and verify standard compliance of PCIe receiver ports in ASICs, add-in cards and motherboards.



Since the release of revision 3.0 of the PCI Express specification, the 8-GT/s interface has been designed into many computer platforms. A common reference clock often is used for PCIe designs, but more and more designs now require a separate reference clock architecture with independent spread spectrum clocking such as a PCIe-over-cable link. When designers use separate reference clocks, they need to compensate for small differences in the clock rate on the transmitter and receiver sides to avoid buffer overflow. Clock compensation can be required even for common reference clock designs on motherboards, in the presence of SSC or when using multiplying phase-locked loops. The PCI Express standard requires this compensation to be accomplished by adding SKP symbols to (or removing them from) the nominal SKP ordered set.



Agilent's new J-BERT N4903B high-performance serial bit-error ratio tester software enables receiver testing in cases where the SKP ordered set length is changed by the device under test in loopback mode. The J-BERT error detector can now ignore SKP ordered sets when counting errors, even when they deviate from the original length sent out by the pattern generator. When engineers debug their designs, they can monitor SKP ordered set counters in the error detector.



For PCIe 3.0 chipset and board designers, our solution's ability to handle adjustments of PCIe 3.0 SKP ordered sets during receiver jitter tolerance characterization fills a critical need, said Michael Fleischer-Reumann, strategic product planner for Agilent's Digital Photonic Test Division. The flexible architecture of our J-BERT, along with our long expertise in PCI Express receiver testing, allowed us, once again, to address emerging test challenges.



With this enhancement, Agilent continues to broaden its complete and accurate PCIe 3.0 receiver test solution, which can be used for characterizing against the base specification as well as the card-electro-mechanical specification.



The Agilent receiver test solution encompasses the J-BERT N4903B high-performance serial BERT, the N4916B de-emphasis signal converter, the N4915A-014 PCIe 3.0-compliant calibration channels, the 81150A or 81160A pulse function arbitrary noise generator, an Infiniium 90000 or 90000 X-Series high-performance oscilloscope, and N5990A-101 and N5990A-301 test automation and link training software. For motherboard testing, the N4880A reference clock multiplier is available.



Benefits of the Agilent PCIe 3.0 receiver characterization solution include:



-Support for PCIe receiver testing with both common and separate reference clocks by the ability to count errors while ignoring SKP ordered set length changes.



-Accurate and repeatable receiver test results enabled by stress calibration software, adjustable pre- and post-cursor de-emphasis, J-BERT's built-in PCIe 3.0-compliant jitter and sinusoidal interference sources, periodic jitter-sweep functionality, a 100-MHz reference clock multiplier and PCIe 3.0-compliant calibration channels.



-Higher R&D efficiency enabled by PCIe 3.0 stress calibration and receiver test automation software and the PCIe 3.0 link-training suite, which controls J-BERT's pattern sequencer to bring the device under test into loopback mode.



-Investment protection enabled by using Agilent instruments that can be repurposed for accurate characterization for multiple gigabit test applications, such as USB, SATA, MIPI M-PHY, TBT and QPI.



Agilent will demonstrate its enhanced PCI Express 3.0 receiver characterization solution at DesignCon 2013, Jan. 28-31, at the Santa Clara Convention Center, Booth 201. Agilent offers a wide selection of high-speed digital solutions, including essential tools to pinpoint problems, optimize devices and deliver results for design and simulation.