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New Generation EDA Software improves Testbench Quality for BSDL Verification

3rd November 2010

ES Admin

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At the 2010 International Test Conference (ITC), GOEPEL electronic, a global leader in JTAG/Boundary Scan solutions, introduces TAP Checker™ a new generation EDA software tool for verification of BSDL (Boundary Scan Description Language) files and validation of JTAG implementations in integrated circuits. The innovative tool suite enables the automatic generation of simulation vectors and test patterns for chip-level validation and verification of IEEE 1149.1 and IEEE 1149.6 compliant implementation. The TAP Checker™ tool is well positioned to support future IEEE test and debug standards due to its modular architecture.

/> “The quality of BSDL files has a fundamental impact on the efficiency of project development for all JTAG/Boundary Scan test and programming applications. GOEPEL electronic’s TAP Checker™ software is the basis for a significantly more flexible and thorough verification compared to what has been available before“, says Heiko Ehrenberg, GOEPEL electronic’s Manager of North American Operations. “As a spin-off of an already industry-proven Computer Aided Test (CAT) software suite, TAP Checker benefits tremendously from existing experience and infrastructure. This strategy also provides for an excellent synergy between chip and board level system test solutions. This new software generation also puts us into a great position to tackle technology driven changes in standards related to test and debug.”

TAP Checker™ is based on modular platform architecture with a central database and individual licensed modules for data import, automatic test vector generation and data export. This structure enables a scalable tool suite that can also support new bus protocols without loosing backward compatibility. After importing the BSDL file a process which includes syntax, semantics, and consistency verification, the user has a multitude of parameterized options, providing the means to generate an optimised testbench.

In addition to IEEE 1149.1, TAP Checker™ also supports IEEE 1149.6 for the test of Advanced Digital Networks. For all operations the tool can insert customer-specific initialization and control sequences in the testbench, significantly improving flexibility.
Options for VHDL (IEEE 1076), Verilog (IEEE 1364) and STIL (IEEE 1450) are available for testbench and test pattern export. As a result the TAP Checker™ outputs can not only be used in any simulators but can be transferred to all market-leading chip testers through a standardized test vector format, helping to improve testbench quality and to increase fault coverage in semiconductor test.
TAP Checker™ is shipping and is available for SOLARIS®, Windows® and LINUX® operating systems.