LeCroy introduces first oscilloscope-based decode solution for PCI Express 2.0 and 3.0

The new PCI Express Decode Annotation capability has widespread application for all versions of PCI Express. It is especially helpful for the emerging PCI Express Gen 3.0 standard, where new silicon physical layer (PHY) links are beginning to be validated before the standard has been finalized. In the early PHY validation stages, the physical layer signals may not exhibit the desired signal fidelity, and a significant amount of physical layer debug must often occur before a specialized protocol analyzer can be used. In addition, it can be difficult to time correlate protocol analyzer and oscilloscope captures; therefore, interpretation of the information from the two different tools could be more time consuming and more error prone. By providing the decoded information as an annotation on the physical layer waveform within the oscilloscope, the protocol and physical layer information is synchronized, and permits easy scrolling and review of the captured data, as is often necessary. Thus, interpretation is easier, faster, and more reliable in the early PHY validation stage.

PCI Express Gen 1.x, Gen 2.0 present their own challenges. Interoperability issues detected at a compliance workshop may be difficult to debug independently with either a protocol analyzer or physical layer compliance test because the problem is often due to correlated physical layer/protocol transmission problems. By showing the link layer protocol decode and the physical layer waveform simultaneously on the oscilloscope, debug time can be dramatically decreased. PCI Express Gen 1.x, widely available in embedded microcontrollers, is used by a wide pool of hardware and systems engineers who may not be familiar with PCI Express. By providing a link layer decode annotation on the oscilloscope, it becomes easier for these engineers to implement this standard in their design, and also assess the relationship between the PCI Express traffic and control lines or other signals in their embedded control system.

The initial data rate for decoding may be set to the common 2.5, 5, or 8 GT/s, PCI Express Gen 2.0 and Gen 3.0 begin handshaking at lower bit rates, and once the link is established, increase to their maximum data rate. The decode algorithm recognizes the different bit rates and decodes appropriately, and supports modes with and without scrambling enabled.