LeCroy Demonstrating SimPASS PE On Cadence Palladium Platforms at CDNLive!

SimPASS PE for PCI Express is the first tool to be available in the new LeCroy SimPASS product line. SimPASS PE allows RTL simulation vector files (that describe PCI Express 3.0 I/O traffic in the pre-silicon phase) to be displayed and analyzed in the same way as hardware-derived trace files in the post-silicon phase. By extracting features that show potential flaws in data and transaction packets from the I/O stream, SimPASS enables developers to more completely test and debug the logic design before committing the design to silicon, a major advance in eliminating design flaws that cause expensive and time-consuming redesign. Major issues facing PCI Express 3.0 developers, such as errors in power state transitions within the LTSSM and improper credit flow exchanges, can be quickly identified, tracked to their source, and resolved, resulting in significantly faster time-to-market and lower development costs in new product development.

Design teams are looking for new ways to simulate I/O more thoroughly. However, this often means more time consuming and extensive testing, said John Wiedemeier, Product Marketing Manager of LeCroy's Interconnect Communications Group. SimPASS PE provides a new capability for PCI Express verification that will help find protocol errors and performance issues much earlier in the design cycle, where they can be fixed with minimal impact on schedule and budget.

SimPASS works by importing raw PCI Express symbol traffic as captured in an RTL simulation. Developers can export RTL simulation vector files from leading electronic design automation (EDA) PCIe® compliance tools, or from their own internally-developed RTL testbench. The symbol traffic files are directly analogous to a trace file captured from hardware, and can be analyzed by SimPASS with all the power and flexibility of a protocol analyzer, helping to determine potential protocol errors. This provides important advantages in identifying and troubleshooting logic design flaws during the simulation and functional verification process, by using the powerful data displays and drill down capabilities of the CATC Trace displays in quickly locating the source of each error. The ability to track down errors using familiar data displays and error identification tools makes the error resolution process simpler and easier for the engineers involved. During any redesign cycle, fixes for bugs (identified in the previous cycle using LeCroy's PETracer trace analysis software) can be verified by testing the fixes during simulation using the SimPASS software.