DDR bus simulator addresses Bit Error Rate challenge

1st October 2014

Keysight Technologies (formerly Agilent)

Mick Elliott

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Datasheet

Keysight Technologies has introduced the DDR Bus Simulator; a tool that generates accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification. The software product, which is available as a new option for Advanced Design System (ADS) 2014.11 from Keysight EEsof EDA, quickly and accurately calculates DQ and DQS eye probability density distributions and BER contours for memory interfaces.

The simulator achieves this through use of statistical simulation, meaning no lengthy or time-consuming bit pattern is needed. Instead, it constructs the eye diagram from the transmitter, channel and receiver impulse responses, and from the stochastic properties of a conceptually infinite non-repeating bit pattern.

Previously available tools constructed eye diagrams using precarious dual-Dirac extrapolation of a limited bit pattern from either a SPICE-like or convolutional channel simulation.

The ADS DDR Bus Simulator offers rigorous DQ and DQS eye calculations to arbitrarily low BER levels, including the 1E-16 contour specified by JEDEC. The simulator accounts for crosstalk and asymmetry between rising and falling transition times, and provides comprehensive timing and voltage margins between the contour and DDR4 receive mask specification.

It allows for three IC model types: built-in, IBIS or circuit models; all of which can be “mixed and matched” in a schematic. The built-in driver and receiver contain de-emphasis and continuous-time linear equalisation capabilities, respectively.