Test & Measurement
Fab feedback for new semi development
In some cases, when developing new integrated devices designers use the initial data they obtain to provide feedback to the fab, requesting a tweak of some process parameter, the better to establish the particular device characteristic for which they are looking. Once the designer is satisfied the device is ready, he or she moves on to a much more detailed sample testing phase.
In aDesigners also typically measure several other AC and transient characteristics, including rise/fall time (tr, tf), switching delay (tdon, tdoff) and reverse recovery time (trr). For power FETs and IGBTs, numerous charge measurements are performed, including total gate charge (QG), pre- and post-threshold gate charge (QGS1, QGS2), drain charge (QGD) and output charge (QOSS). Curve tracers’ limited applicability becomes increasingly apparent and they have been largely replaced with modern digital semiconductor parameter analysers (SPAs) for these types of measurements. Until recently, even SPAs were limited by insufficient power and capability for such applications. For example, many lacked the speed or power necessary to capture many of the charge characteristics. A difficult test called Dynamic On Resistance (sometimes referred to as “current collapse” in a gallium nitride power HEMT) is one good example. The device must be biased to full breakdown voltage, typically 600V, then switched to full ON current, often as high as 50A, all while monitoring the ON resistance for rapid changes in RDS(ON). These changes can occur as rapidly as microseconds and can continue for milliseconds. Keithley’s newest high power SMUs incorporate numerous digital enhancements, such as high speed digitisers, intended to make it easier for designers to capture important data.
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Other equipment used at the sample testing stage includes pulse generators and oscilloscopes, IR cameras, EMF Test, and wafer probers. In some cases, the devices will be packaged to allow for easier testing in a specially designed test fixture rather than at the wafer level.
You can read the rest of this article in the September issue of Electronic Specifier Design by clicking here.