JTAGLive takes Command of MicroCores for PCB Test & Debug

5th March 2012

ES Admin

0 0

JTAGLive is pleased to announce the introduction of a new series of debug tools for DSP and microprocessor systems utilising a variety of RISC and DSP cores. Using JTAGLive CoreCommander engineers can activate the OCD (On-Chip Debug) modes of a range of popular cores to affect ‘kernel-centric’ testing.

While many devices are now equipped with JTAG (IEEE Std. 1149.1) boundary-scan registers (BSRs), which are used extensively to provide test access into digital and mixed-signal designs, a significant number of microprocessors and DSPs can be found with deficient or even non-existent boundary-scan test registers. For the electronics test engineer this can, at best, be ‘frustrating’ as they look to employ alternative methods for testing the ’processor and/or associated cluster/peripheral components.

CoreCommander routines are ideal for diagnosing faults on ‘dead-kernel’ boards in either design debug or repair, since no on-board code is required to set memory reads and writes. Boundary-scan deficient parts can also be better utilised during production test, as CoreCommander-driven functions increase fault coverage. Since CoreCommander is Python-based it complements perfectly the JTAGLive Script product, allowing access to mixed-signal parts such as ADCs and DACs and also synchronised testing to full boundary-scan devices.

The solutions, available now, take control of key processor core functions using the built-in emulation/debug functions of the ‘processor core and are designed by test engineers for use by test engineers. JTAG CoreCommander products are quick to learn and easy to use due to the dual modes of operation, namely ‘Interactive’ or ‘Python embedded’:

• Interactive mode allows the user to select a supported device within a design and ‘manually’ select register access commands or full memory reads and memory writes from the interactive window and via a supported controller to the target design. Sequences of commands can be exported from the interactive window and replayed as part of a Python script.

• Python-embedded mode uses a similar structure to that featured in the JTAGLive Script product, allowing CoreCommander functions to be embedded into Python code to create re-usable test modules for specific tests.

Examples are provided that allow the user to create RAM tests or flash memory programming functions through core operation.