Improving system level test productivity

Through Cadence’s support for the standard, customers creating complex automotive, mobile and server designs can confidently adopt the Perspec System Verifier to automate SoC coverage closure and achieve up to ten times improved system level test productivity.

The Perspec System Verifier provides an abstract model based approach for defining the SoC use cases from the PSS model and uses Unified Modelling Language (UML) activity diagrams to visualise the generated tests.

The Perspec System Verifier tests are optimised for each tool in the Cadence Verification Suite, including Cadence Xcelium Parallel Logic Simulation, the Palladium Z1 Enterprise Emulation Platform and the Protium S1 FPGA-Based Prototyping Platform. Additionally, the Perspec System Verifier integrates with the Cadence vManager Metric-Driven Signoff Platform to support the new use-case coverage in the PSS.

Finally, the Perspec System Verifier generates tests that can utilise Cadence Verification IP (VIP), enabling re-use of the verification content via the PSS methodology, to achieve faster, more thorough SoC verification that requires less effort.

“Cadence’s support for the Accellera Portable Test and Stimulus Specification is critical for driving automotive IC innovation in our business,” said Thorsten Klose, Lead Principal Engineer, Functional Verification at Infineon. “We’ve had proven success creating SoC tests with the Cadence Perspec System Verifier and managing verification closure with the vManager Metric-Driven Signoff Platform, enabling us to improve overall verification productivity by up to three months. With Cadence’s support for the new standard, we can execute with confidence and enable industry collaboration for verification of our new automotive application design projects.”

Paul Cunningham, Corporate Vice President and General Manager of the System & Verification Group at Cadence added: “The electronics industry has previously faced many challenges with verifying SoCs more effectively, and our collaboration with the Accellera Systems Initiative is the start of a new phase in the electronics industry that addresses these challenges. By providing support for the Portable Test and Stimulus Specification 1.0, the Perspec System Verifier and the broader Cadence Verification Suite deliver a production-proven SoC test generation toolset to improve design quality and accelerate verification.”

The Perspec System Verifier is part of the Cadence Verification Suite. Together, they support the company’s System Design Enablement strategy, which enables system and semiconductor companies to create complete, differentiated end products more efficiently. The Verification Suite is comprised of core engines, verification fabric technologies and solutions that increase design quality and throughput, fulfilling verification requirements for a wide variety of applications and vertical segments.