Embedded World 2014: JTAGLive tools on parade

Designs with only a few, even just one or two, JTAG devices can also greatly benefit during all stages of the life cycle. A toolset capable of handling even the most complex boundary-scan designs, however, often is not economically feasible for a company that only uses a few JTAG devices in its designs.

It works with or without design net list data and can be used to test interconnects (from individual nets to an entire board), logic clusters, memories and more. Studio also includes device programming features that support JAM/STAPL and SVF data formats for CPLD and [FPGA] configuration PROM programming.

JTAG CoreCommander is a simple, low-cost system that uses microprocessor core emulation modes to aid hardware validation and board (PCBA) testing. The easy user interface and low-cost JTAG interface hardware will enable users to construct read and write sequences from the processor core to embedded or external peripherals and peripheral controllers in minutes.

Python support further enables usersto construct more sophisticated test sequences using CoreCommander Python libraries as required - all from within the user-friendly JTAGLive environment.Supported Cores include ARM 7/9/11, Cortex, Marvell PXA, Microchip PIC32, TI C2000, Freescale PowerPC/Nexus, and Infineon TriCore.