Agilent Technologies Introduces DDR3 Test Suite and claims Industry's Fastest Full Channel Logic Analysis Tool

This test suite is ideal for R&D engineers integrating a memory controller with the DDR memory devices on the memory subsystem for interoperability testing. This is the key challenge for most designers as the memory controller design can be developed in-house or acquired from third-party IP.

The use of DDR3 has significantly increased in both the computer and embedded memory design market. DDR3 provides higher performance and lower power compared to DDR2, which encourages many memory designers to adopt DDR3 memory devices in their board design.

Today's computer speeds and complexities demand that engineers take test and measurement requirements into account when writing specifications so that the technology will be testable. Measurements are central to the diagnosis of a problem and when proving the correct fix has been made. Agilent contributes to the standards groups, such as JEDEC, to ensure design for test is occurring and guaranteeing that Agilent products measure for specification compliance.

* The 16962A logic analysis module with 2.0GT/s state speed and 2GHz trigger sequence speed enables full capability to reliably trigger and capture DDR3 1600 signals. When used with the new DDR3 probing solution and analysis software tool, this module provides full test capability for system integration in the memory industry.
* The W3630A Series DDR3 BGA probe provides direct access to the balls of the DRAM with low loading and minimal impact to signal integrity on embedded system design. The probes are used with oscilloscopes and logic analyzers to perform physical layer and functional test.
* The N4835A DDR3 slot interposer enables up to 1.6GT/s high-speed memory bus access through a slot connector in the server and desktop application. The DDR3 slot interposer provides a non-intrusive probing design for quick and easy access to industry-standard DDR3 DIMM.

In addition to announcing a complete DDR solution for the industry, Agilent is introducing its first B4622A DDR2/3 protocol compliance and analysis tool. This tool provides timing and protocol violation check, an automated physical address trigger setup tool, and overview of system performance through bus statistic information and histogram view of address access. The tool will help reduce memory designers' troubleshooting time and increase productivity and efficiency in DDR design validation work.

The industry needs a complete solution for DDR functional validation from both a probing and analysis point of view, said Perry Keller, Memory program manager at Agilent's Digital Test Division and member of the JEDEC Board of Directors. Agilent's new probing solution meets both the computer and embedded design market needs. The new protocol compliance and analysis tool provides insights to the memory bus activities to quickly identify problem areas in the design, and allows our customers to launch their products faster into their markets.

The Agilent N4835A DDR3 slot interposer supports industry standard 240-pin DDR3 DIMMs. The B4622A DDR2/3 Protocol Compliance and Analysis tool works with all the current Agilent's DDR2/3 solution.