Next generation of memory ICs get test upgrade

As internet-enabled mobile devices and their supporting servers continue to handle larger amounts of data, manufacturers of high-speed, high-capacity memory chips need cost-efficient test solutions that will help them get their newest products to market faster, including emerging DDR4-SDRAM and LPDDR4-SDRAM semiconductors. Advantest’s T5503HS system gives memory manufacturers the functionality they need while also reducing their cost of test.

The new system can reach testing speeds of up to 4.5Gbps, fast enough to handle the 4.266Gbps maximum operating frequencies of today’s most advanced double-data-rate SDRAM semiconductors. To ensure maximum test speeds, the system automatically generates cyclic redundancy check (CRC) codes and CA parity codes to match the I/O data rates and address of the devices under test. This streamlines the development of new test programs, reducing customers’ workloads and improving the time to market for new semiconductor designs.

It can perform parallel testing of up to 512 DDR4-SDRAM devices, enabling economical, production-volume testing. In addition, currently installed T5503 testers can be upgraded on site, which extends customers’ return on investment (ROI) as next-generation devices are introduced.

Additionally, the tester’s real-time source-synchronous function allows it to achieve higher yields and higher throughputs. Incorporated in the system hardware is a timing-training capability that enables the tester to pinpoint solutions faster than conventional systems on today’s market, reducing test time in comparison to software-based systems.

Other functions such as individual level settings, I/O dead-band canceling, and data-bus inversion (DBI), which helps to further reduce data-transmission delays, make the T5503HS ideally suited for testing all high-speed memories.