Search results for "CUI Devices"

Mouser Electronics has published a new eBook in collaboration with Cinch Connectivity Solutions.

This week, at the 2024 IEEE International Electron Devices Meeting (IEDM), imec demonstrates the three critical building blocks of a superconducting digital circuit: NbTiN-based interconnects; Josephson junctions; and MIM capacitors.

Nexperia released a new family of next-generation fixed-direction voltage level translators ideal for use with some of the most commonly used push-pull data interfaces (including UART, SPI and JTAG protocols) as well as for general purpose input/output (GPIO).

Advantest Corporation will showcase its latest test solutions atSEMICONJapan 2024 on Dec. 11-13 at the Tokyo Big Sight in Tokyo, Japan.

Crypto Quantique has upgraded its QuarkLink IoT device security platform with a hybrid post-quantum cryptographic algorithm.

Renesas has introduced the RAA489118 buck-boost battery charger and the RAA489400 USB Type-C port controller.

Semiconductor test equipment supplier Advantest has announced an integrated test cell designed to maximise die-level test yields for wide-bandgap (WBG) devices essential to power semiconductors.

Ultrasonic DIE bonding is a fast, clean, and efficient technology increasingly utilised in the semiconductor industry for the assembly of heat sensitive microelectronic DIE’s. This method leverages high-frequency ultrasonic vibrations to create a reliable bonds between semiconductor DIEs and substrates, significantly reducing thermal stress. The advantages of ultrasonic DIE bonding include rapid processing times, low temperatures, and excel...

NEC has expanded its lineup of optical transceivers for 100Gb/s transmission, and has started selling the new ‘100G QSFP28 ZR4 BiDi,’ which extends transmission distance to 80km.

At the 2024 IEEE International Electron Devices Meeting (IEDM), imec, a leading research and innovation hub in nanoelectronics and digital technologies, presents a new CFET-based standard cell architecture containing two rows of CFETs with a shared signal routing wall in between.