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Cadence Design Systems, Inc. has announced that Panasonic Corporation has deployed the Cadence Palladium XP Verification Computing Platform, part of the Cadence System Development Suite, to speed the design of Systems-on-Chip (SoCs) for next-generation digital consumer products such as Smart TVs and video recorders. Palladium XP unifies simulation, acceleration and emulation capabilities in a single environment enabling hardware-software system ...

At the International Electron Devices Meeting in San Francisco imec’s advanced CMOS research program reports promising advances in scaling logic, DRAM and non-volatile memory. A new device based on non-silicon channels was realized to scale high-performance logic towards the sub-20nm node. Moreover, imec developed low-leakage capacitors allowing DRAM to be pushed to the 2x nm node. And the switching mechanism of resistive RAM for next-generatio...

Today, imec and Panasonic Inc. have entered into the next phase of a comprehensive and broadened collaboration agreement for joint R&D on healthcare, wireless communication, flexible electronics and advanced CMOS process technologies. The signing ceremony at the Panasonic Headquarters in Osaka (Japan) today was endorsed by the presence of His Royal Highness Prince Philippe of Belgium.

Imec sets major step towards 20nm half pitch interconnects with the realization of electrically functional copper lines embedded into silicon oxide using a spacer-defined double patterning approach.