Search results for "TSMC"

Tensilica has announced that it has optimized the MP3 decoder for its Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. This MP3 decoder now runs at the lowest power and is the most efficient in the industry says Tensilica, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65nm LP process (including memories). This makes Tensilica’s Xtensa HiFi 2 Audio Engine ideal for adding MP3 ...

The National Microelectronics Institute (NMI), the trade association representing the semiconductor industry in the UK and Ireland, in collaboration with the UK’s nanoCMOS project, is to hold Europe’s first international conference dedicated to the subject of CMOS variability. The conference will take place on 23rd October at the Royal College of Physicians, London.

Mentor Graphics announced it has expanded the use of low power verification capabilities in TSMC’s Reference Flow 11 to address today’s complex integrated circuit (IC) low power functional verification requirements. The Mentor® low power verification tool suite includes the Questa® functional verification platform, the 0-In® CDC (Clock Domain Crossing) and the 0-In Formal tools and the FormalPro™ equivalence checking tool.

Tensilica has announced that it has optimized the MP3 decoder for its Xtensa HiFi 2 Audio Engine and Diamond Standard 330HiFi processor core. This MP3 decoder now runs at the lowest power and is the most efficient in the industry says Tensilica, requiring just 5.7 MHz when running at 128Kbps, 44.1 KHz and dissipating 0.45 mW in TSMC’s 65nm LP process (including memories). This makes Tensilica’s Xtensa HiFi 2 Audio Engine ideal for adding MP3 ...

Multi-project wafer services company MOSIS has teamed up with IBM¹s silicon foundry to offer 90nm chip process technology on a shared-wafer basis. The MPW service will give many companies that have previously found sub-micron silicon fabrication costs prohibitive access to these technologies for as little as 10% of the price of a dedicated wafer run.

SiliconBlue has announced a new class of single-chip, ultra low-power FPGA devices, that set a new industry standard for price, power and space along with unprecedented ASIC-like logic capacity for battery-powered, handheld consumer applications. Manufactured on TSMC’s 65nm LP (low-power) standard CMOS process, the new single-chip iCE family of FPGAs incorporate the company’s proprietary NVCM (Non-Volatile Configuration Memory) technology, e...

Staccato Communications has announced the availability of the Ripcord2 family of single-chip, all-CMOS solutions targeted for WiMedia UWB and Wireless USB applications. This second-generation family is the industry’s first implementation utilizing 65nm CMOS process technology, and offers a quantum leap in power consumption, size and integration over existing solutions.

Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, announced today that TSMC used Quartz™ DRC for physical verification of its 28-nanometer (nm) product qualification vehicle (PQV) test chip. PQVs are representative of design data customers will use in production designs. By designing and manufacturing the PQV test chip, TSMC offers its customers greater confidence in achieving silicon success in its 28-nm proce...

ARM has announced the development of two Cortex-A9 MPCore hard macro implementations for the TSMC 40nm-G process, enabling silicon manufacturers to have a rapid and low-risk route to silicon for high-performance, low-power Cortex-A9 processor-based devices. The speed-optimized hard macro implementation will enable devices to operate at frequencies greater than 2GHz.

Synopsys, Inc. today announced that TSMC has given Phase I Certification to Synopsys design implementation tools for its 20-nm process. TSMC certified the tools for its 20-nm design rule manuals and SPICE models. Certified products include Synopsys' IC Compiler for physical design; IC Validator for DRC and LVS; StarRC for extraction; and Galaxy Custom Designer for custom implementation.