Search results for "EDA"

Cadence Design Systems, Inc announced that its digital and custom/analog tools have achieved V0.9 Design Rule Manual (DRM) and SPICE certification from TSMC for its 16FF+ process, enabling systems and semiconductor companies to take advantage of the 15 percent speed improvement with the same total power compared to 16nm FinFET, or 30 percent total power reduction at the same speed compared to 16nm FinFET. 16FF+ V1.0 certification is on track to b...

ARM and Synopsys, Inc have signed a multi-year subscription agreement that expands Synopsys' access to a broad range of ARM intellectual property (IP) and related technologies to enable optimization of Synopsys tools and methodologies for ARM-based system-on-chips (SoCs). Through this agreement, Synopsys has pre-production access to ARM Cortex processors for the ARMv8-A and ARMv7-A architectures, ARM Mali graphics processors, ARM CoreLink system ...

Keysight Technologies has introduced the DDR Bus Simulator; a tool that generates accurate Bit-Error-Rate (BER) contours for the JEDEC DDR memory bus specification. The software product, which is available as a new option for Advanced Design System (ADS) 2014.11 from Keysight EEsof EDA, quickly and accurately calculates DQ and DQS eye probability density distributions and BER contours for memory interfaces.

Wideband signal generation and analysis and research on 5G and mmW communication are just two of the test technologies and solutions that Keysight Technologies will bring to its show debut at European Microwave Week in Rome (Oct 7-9). The test and measurement company will host workshops and demonstrate test solutions in four key areas: aerospace and defence, device characterisation, simulation using Keysight’s Advanced Design System (ADS), ...

A 1.6 GBit per second digital module from Advantest incorporates a new feature called Functional Test Abstraction Plus (FTA+) to achieve protocol-aware testing in which the tester communicates directly with the devices under test (DUT) in each IC’s protocol language. Advantest says that the T2000 digital module will improve efficiency in testing system-on-chip (SoC) devices on the T2000 test platform.

Agilent Technologies’ EEsof EDA W1462 SystemVue FPGA Architect now supports on-board FPGA design and simulation with the Agilent M9703A AXIe wideband digital receiver/digitiser. The new modelling and simulation capability reduces development time for research and design validation teams working on early system prototyping and development of advanced multichannel applications.

Semiconductor companies developing DDR controller IP, those developing DRAM chips and DIMMs, and OEMs integrating the controller and DIMM into a system using PCB technology can now use Agilent Technologies’ Advanced Systems DDR4 Compliance Test Bench for a complete workflow from simulation of a candidate to measurement of the finished prototype.

Cadence Design Systems Inc announced the signing of the first EDA (Electronic Design Automation) Technology Access Agreement with ARM Holdings plc that includes access to the ARM Cortex-A50 processor series, based on the ARMv8-A 64-bit architecture. This agreement also provides access to ARMv7 32-bit processor technology, ARM Mali GPUs (graphic processor units), System IP and ARM Artisan libraries. This collaboration further enables ARM and Caden...

Invionics took the wraps off the VRDM Development Platform that layers a rapid development interface on top of Verific’s industry-standard, IEEE-compliant SystemVerilog and VHDL parsers.

Altium Limited has introduced the WEBENCH Altium Connector, a collaborative effort between Altium and Texas Instruments (TI) to blend TI’s award-winning WEBENCH power design and simulation tools with Altium’s leading EDA tool suite Altium Designer. This powerful platform provides design engineers with the first end-to-end analog circuit design and simulation environment, including everything from creating the power supply, simulating ...