Search results for "EnSilica"
IoT reference platform improves next-gen wearables
EnSilica and sureCore have announced that EnSilica has developed sureCore’s new, ultra-low power IoT reference platform targeted principally at the development of the next generation of wearable consumer and medical applications.With proven expertise in low power SoC design for battery powered applications, EnSilica’s experienced silicon team is able to deliver a complete, turn-key service covering complex digital and analog/RF techno...
Design centre for RF applications established near Oxford
Independent provider of semiconductor solutions and IP, EnSilica has further expanded its network of specialist design centres with the establishment of a facility near Oxford (UK) focusing on RF and low power sensing applications.The RF and low power sensing design centre will be headed up by Alan Wong, formerly the IC Design Director at Frontier Microsystems.
Multi-project wafer customers provided with configurable IP solutions
EnSilica has teamed with BaySand, to provide customers of BaySand’s newly launched ASIC UltraShuttle-65 Multi-Project Wafer (MPW) with a range of IP solutions that can be configured to their specific application requirements. The IPs will comprise EnSilica’s eSi-RISC processor cores, eSi-Connect processor peripherals, eSi-Crypto encryption and eSi-Comms communications IP solutions as well hardware accelerators.
EnSilica & Micrium port µC/OS-III RTOS to eSi-RISC processor cores
EnSilica have partnered to successfully port Micrium’s µC/OS-III RTOS to EnSilica’s family of eSi-RISC processor cores. Micrium’s µC/OS-III is available on eSi-RISC with immediate effect. In addition, Micrium’s range of communication software, including its USB host/USB device and TCP/IP networking protocol stack, has been ported to EnSilica’s eSi-RISC.
Cryptographic IP enables Car2x applications
EnSilica has launched the eSi-ECDSA cryptographic IP designed to help meet the high security communication and latency requirements of automotive Car2Car and Car2Infrastructure (Car2x) applications that form part of today’s emerging Intelligent Transport Systems.
Increasing demand puts EnSilica on recruitment path for engineers
EnSilica has announced that it is planning an immediate recruitment drive for additional engineering staff following a further year of increasing demand and continued growth. In addition, in a further commitment to its ongoing growth strategy, EnSilica has also appointed Mark Hodgkins as Executive Chairman to its Board of Directors and David Doyle as its latest Sales Director.
Kalman Filter acceleration IP core suits ADAS
EnSilica has launched a Kalman Filter acceleration IP core for use in situational awareness radar sensors for ADAS, such as electronic stability control systems, pre-crash impact mitigation, blind spot detection, lane departure detection and self-parking.
Combination of eSi-RISC & ThreadX suited to IoT applications
EnSilica and Express Logic have collaborated to port Express Logic’s popular ThreadX RTOS to EnSilica’s eSi-RISC family of silicon-proven, highly configurable embedded processor cores.ThreadX ease-of-use is facilitated by its intuitive, highly functional API and advanced, instant-on RTOS features.
enSilica, Anglia in UK/Ireland tie-up
EnSilica has appointed Anglia Components as its business development partner in the UK and Ireland for its eSi-Modules family of FPGA-based system-on-modules. Anglia will target the eSi-Modules at key vertical industry sectors including utilities, smart cities, oil and gas, access control, medical devices, IoT, industrial internet and telematics.
Processor targets WiFi, LTE Cat-0 & other IoT standards
Targeting applications requiring a high level of processing per MHz and low power consumption in a small footprint, the the eSI-32X0MP scalable, asymmetric multicore processor has been released by EnSilica. The processor, which expands the company’s eSi-RISC family, is suitable for WiFi, LTE Cat-0 and other IoT standards as well as scalable sensor, Gbit security protocol and solid state disk levelling algorithm processing.