Search results for "ASIC"

Oscium's New iMSO-104 Oscilloscope Powered By Cypress's PSoC 3 Device Turns iPod touch, iPhone and iPad into Easy-to-Use Mixed Signal Scopes PSoC 3 Handles Apple's Proprietary Interface For iOS Devices While Processing Incoming Analog and Digital Signals for Intuitive Scope System That's Both Affordable and Portable

Cypress Semiconductor Corp. and Bhubaneswar Institute of Technology (BIT) announced a partnership to set up a Programmable System on Chip (PSoC) lab at Bhubaneswar. The agreement was signed at Cypress headquarters in San Jose, California, by BIT Chairman, Dr. Rabi Mahapatra and Cypress University Alliance Director, Patrick Kane.

Cypress Semiconductor Corp. today announced that semiconductor industry veteran, Kazuyoshi “Kazu” Yamada, has been named Country Manager of Cypress Japan, reporting to Senior Vice President of Worldwide Sales, Ben Lee. He replaces Hitoshi Yoshizawa, who retires after a distinguished career of 40 years, the last four as Cypress Japan Country Manager.

At next week’s International Solid-State Circuits Conference (February 19-23, 2012, San Francisco, USA), imec and Holst Centre present 14 papers on low power design for wireless communication and wireless sensor networks, and organic electronics. Over the week, imec and Holst Centre will issue several news releases showcasing recent important breakthroughs in these different research domains.

Maia EDA has today announced the availability of the Maia functional verification tool. Maia uses a description of the expected behavior of a device to automatically create a complete self-checking reactive testbench, so freeing engineers from the time-consuming, complex, and error-prone task of manual testbench creation. The tool has been designed to enable both engineers and non-engineers to quickly verify modules and sub-systems, and is initia...

Cadence Design Systems (India) Pvt Ltd., a subsidiary of Cadence Design Systems, Inc. (NASDAQ: CDNS), announced that Open-Silicon, Inc., a leading semiconductor company focused on ASIC design, develop-to-spec, and derivative ICs, has successfully taped out a breakthrough high-performance processor at over 2.4GHz under typical conditions utilizing the Cadence® Silicon Realization product line. Open-Silicon completed the entire design using Cadenc...

Cadence today announced significant new advancements to help boost verification productivity for ASIC and FPGA designers. Coupled with full support for the emerging Accellera Universal Verification Methodology (UVM) 1.0 industry standard, the 600-plus new capabilities expand the scope of metric-driven verification (MDV) to help engineers achieve faster, more comprehensive verification closure and Silicon Realization.

Cadence Design Systems, Inc. (NASDAQ: CDNS), a global leader in electronic design innovation, and Xilinx today introduced the new Xilinx IP Ecosystem microsite, a unified site meant to increase FPGA and ASIC designers’ visibility to the latest IP supporting the Xilinx programmable platform.. The microsite, developed as part of a broad initiative announced by Xilinx to transform and enable its ecosystem of third-party providers, is part of the C...

EnSilica, a leading independent provider of front-end IC design services, and Pebble Bay, a leading embedded systems development consultancy, are collaborating to target the automotive electronics design market by porting ERIKA Enterprise, the free-of-charge, open source RTOS for automotive systems, to EnSilica’s family of highly configurable and low-power eSi-RISC soft processor cores. The port provides proof of the suitability of EnSilica’...

EnSilica, a leading independent provider of front-end IC design services, has announced a special licensing deal to encourage existing 8051 licensees to switch their next ASIC design start to an eSi-1600 16-bit soft processor core. For all enquiries received before 31st January 2011 and subject to Terms and Conditions, EnSilica is offering to match their 8051 license fee.