Search results for "ASIC"
Altera Unveils 28-nm Stratix V FPGA Family
Altera Corporation announced its next-generation 28-nm Stratix V FPGA family, the industry's highest bandwidth FPGA. Offering up to 1.6 Tbps of serial switching capability, Stratix V FPGAs leverage a myriad of new technologies and a leading-edge 28-nm process to reduce the cost and power of high-bandwidth applications.
Altera Quartus II Software Version 11.0 Features the Production Release of Qsys System Integration Tool
Altera announced the release of its Quartus II software version 11.0, the industry’s number one software in performance and productivity for CPLD, FPGA and HardCopy ASIC designs. Version 11.0 features the production release of Altera's next-generation system integration tool, Qsys. The new Qsys tool features the industry’s first FPGA-optimized network-on-a-chip (NoC)-based interconnect delivering up to 2X higher interconnect performance comp...
Altera Starts Production Shipments of the Industry's First FPGAs with Integrated 11.3-Gbps Transceivers
Altera today announced it has started shipping in production its Stratix® IV GT EP4S100G2 FPGA, the industry's first FPGA featuring integrated 11.3-Gbps transceivers. Stratix IV GT FPGAs are the only single-chip devices available today that meet the high-speed bandwidth requirements for next-generation framer, MAC, bridging and switching applications for 100-Gigabit Ethernet (GbE) and 100-Gigabit Optical Transport Networks (OTN). Altera's pro...
Altera's RapidIO IP Core Passes RIOLAB Device Interoperability Testing
Altera Corporation has announced its RapidIO MegaCore function, version 9.0, successfully passed RIOLAB's Device Interoperability Level-3 (DIL-3) testing. Altera is the first FPGA vendor to offer a Serial RapidIO intellectual property (IP) core that is fully qualified by RIOLAB.
Altera Accelerates FPGA Design Productivity in Quartus II Software Version 10.1 with Next-Generation System-Integration Tool
Altera announced the release of its Quartus II development software version 10.1, the programmable logic industry's number-one software in performance and productivity for CPLD, FPGA and HardCopy® ASIC design. The Quartus II Subscription Edition software version 10.1 includes the availability of a beta version of Qsys, Altera's next-generation system-integration tool, which features the industry's first FPGA-optimized network-on-chip-based inter...
MAX13450E/51E: RS-485 transceivers with software-/pin-configurable termination resistors allow remote network configuration
Maxim introduces the MAX13450E/MAX13451E, RS-485 transceivers that integrate software-/pin-selectable, dual-termination (10ohm/120ohm) resistors to simplify RS-485 network configuration. These transceivers are well suited for industrial control equipment, IP camera installations, and other RS-485 network applications.
MAX15048/49: Three-output DC-DC controllers with tracking/sequencing reduce power-management cost for 40nm logic devices
Maxim introduced the MAX15048/MAX15049, low-cost, three-output, synchronous step-down controllers with tracking (MAX15048) or sequencing (MAX15049) options. Designed to meet the tight tolerances of small-geometry logic devices, these controllers drive external MOSFETs to deliver a regulated 0.6V to 19V output voltage and up to 15A of load current per output. Additionally, integrated tracking/sequencing allows customers to seamlessly control core...
Lattice’s “Power 2 You” Can Help Designers Reduce Board Design Cost And Complexity
Lattice Semiconductor announced the availability of a hard copy print version of the “Power 2 You” book that provides designers with 150 pages of technical details and design considerations for implementing common circuit board power management functions. The author is Srirama (“Shyam”) Chandra, a widely published author and recognized authority on power management.
Power management system requirements
Many companies offer integrated hot-swap controllers that use a MOSFET to control how fast the current flows into the board’s hold up capacitor. With considerations for the variances in input capacitances of the hot-swap components, the controller timing can be set to ensure that the current does not exceed the capacity of the system, or the safe operating conditions for the control the MOSFET.
Wipro Technologies Selects Lattice MachXO PLDs For New Server Platforms
Lattice Semiconductor announced that Wipro Technologies (NASDAQ: WIT), one of the largest providers of design services for integrated business, technology and process solutions, has selected the MachXO™ PLD family for use in their new server platforms. The MachXO device performs many of the general purpose I/O expansion, interface bridging and power-up management functions required for the new server designs.