Multitest’s Solution for 3D Packages Released to Production

Our unique product portfolio enables us to partner with our customers to develop comprehensive solutions for this emerging packaging technology that we see as a major strategic initiative in the semiconductor industry.”

The fully integrated setup consists of a Multitest InStrip3D, a test interface board and a contacting solution based on vertical spring technology. The system will be used for electrical test partial stacks during assembly of a mobile SoC.

The InStrip3D utilizes the experience gained from a well-established installed base of high-parallel InStrip/InMEMS solutions. The architecture of the InStrip allows the configuration of the system to meet the special requirements of partial stack test with respect to the extremely sensitive bare dies.

Multitest’s contactor division developed a solution that ensures reliable contacting yield, but only requires a minimum contact force in order to avoid stress on the extremely sensitive bare dies.

The integrated test solution uses a Multitest load board, leveraging the industry-leading fabrication capabilities for fine-pitch, high layer count PCBs to support this 0.4 mm pitch array application in a high pin count multi-site configuration. In close cooperation with the customer, the mechanics of the test were redesigned to accommodate the increased forces from the highly dense pogo array of approximately 6000 pins.

Combining the engineering expertise and capabilities of all three product groups, Multitest developed a fully integrated solution that optimally solves the challenges of a highly sensitive device in a cost efficient multi-site setup. The final Plug & Yield solution enables highly-parallel electrical in-process test of stacked dies during the assembly process of 3-D packages.

With the growing importance of 3-D integration, Multitest sees a great need for cost-efficient in-process test during the package assembly. The current concept of KGD and final test before shipment, does not cover the risk during the assembly of multiple dies.

James Quinn asserts: “Initially 3D packaging created challenges in wafer level processes, such as deep silicon etch and wafer processing. With these challenges being addressed, the industry now faces the need to develop advanced test strategies. Insufficient test strategies will be a hurdle for a broader acceptance of 3D integration, particularly when it comes to TSV. At the same time we are convinced that smart approaches for optimal test insertion points will make test a key differentiator.”

Multitest will display the InStrip3D at the Open House in Santa Clara, from July 10-12, 2012. High parallel test of 3D packages also will be part of the presentation given by Bernhard Lorenz, Vice President Engineering, at the Test Vision 2020 Conference held in conjunction with SEMICON West.