Low-jitter clock generator with DC to 2.05 GHz frequency range

The instrument is ideally suited to demonstrating a system's performance with a nearly ideal clock, and for understanding a system's susceptibility to a compromised clock. The CG635 has the frequency range, precision, stability, and jitter-free performance needed to fulfil all such clock requirements.

The instrument generates extremely stable square-wave clocks between 1 µHz and 2.05 GHz. Its high frequency resolution, low jitter, fast transition times, and flexible output levels make it ideal for use in the development and testing of virtually any digital component, system or network.

Clean clocks are critical in systems that use high-speed ADCs or DACs. Spurious clock modulation and jitter create artefacts and noise in acquired signals and in reconstructed waveforms. Clean clocks are also important in communications systems and networks. Jitter, wander, or frequency offsets
can lead to high bit error rates, or to a total loss of synchronisation. The CG635 can provide the clean, stable clocks required for the most critical applications.

The CG635 has several clock outputs. The front-panel Q and -Q outputs provide complementary square waves at standard logic levels (ECL, PECL, LVDS or +7 dBm). The square-wave amplitude may also be set from 0.2 V to 1.0 V, with an offset between -2 V and +5 V. These outputs operate from DC to 2.05
GHz, have transition times of 80 ps and a source impedance of 50 ohms, and are intended to drive 50-ohm loads. Output levels double when these outputs are unterminated.

The front-panel CMOS output provides square waves at standard logic levels. The output may also be set to any amplitude from 0.5 V to 6.0 V. The CMOS output has transition times of less than 1 ns and operates at up to 250 MHz. It has a 50-ohm source impedance and is intended to drive high impedance
loads at the end of any length of 50-ohm coax cable.

A rear-panel RJ-45 connector provides differential square-wave clocks on twisted pairs at RS-485 levels (up to 105 MHz) and LVDS levels (up to 2.05 GHz). This output also provides ±5 VDC power for optional line receivers (CG640 to CG649). The clock outputs have 100-ohm source impedances and are
intended to drive shielded CAT-6 cable with 100-ohm terminations. The differential clocks may be used directly by the target system, or with optional line receivers that provide complementary logic outputs on SMA connectors.

The standard crystal timebase has a stability of better than 5 ppm. The CG635's 10 MHz timebase input allows the instrument to be phase-locked to an external 10 MHz reference. The 10 MHz output may be used to lock two CG635s together.

The clock phase can be adjusted with high precision. The phase resolution is 1( for frequencies above 200 MHz, and increases by a factor of ten for each decade below 200 MHz, with a maximum resolution of one nano-degree. This allows clock edges to be positioned with a resolution of better than 14 ps
at any frequency between 0.2 Hz and 2.05 GHz.

The timing of clock edges can be modulated over ±5 ns via a rear-panel time-modulation input. The input has a sensitivity of 1 ns/V and a bandwidth from DC to over 10 kHz, allowing an analogue signal to control the phase of the clock output. This feature is very useful for characterising a system's
susceptibility to modulation and jitter.