LeCroy - Stand-alone DDR3 Protocol Analyzer

16th February 2011

ES Admin

0 0

LeCroy Corporation, the worldwide leader in protocol test solutions, today introduced a new low-cost platform that provides comprehensive DDR3 bus and JEDEC timing analysis. LeCroy’s Kibra™ 380 is the industry's first true, standalone protocol analyzer for DDR3, combining waveform views and state listings, with dedicated trigger logic to allow improved visualization of DDR3 state transitions and protocol violations. Designed to lower the cost of testing for developers of DDR3 memory systems, the Kibra 380 eliminates the need for costly logic analyzers while simplifying setup and shortening validation cycles.

/> Cost and complexity are the biggest hurdles validation teams face as they begin testing memory systems. Today's DDR3 design teams are searching for test approaches that do not require JEDEC preprocessor hardware combined with high-end logic analyzer platforms. said Michael Romm, VP of Product Development at LeCroy's Protocol Solutions Group. The Kibra 380 replaces these monolithic systems with a standalone bus analyzer that includes all the essential triggering on JEDEC violations while simultaneously capturing and displaying timing waveforms, decoded state listings, performance and utilization statistics.

The Kibra 380 incorporates traditional waveform views as well as decoded state listings for comprehensive protocol analysis. Specialized trigger logic can identify over 65 JEDEC timing and command violations across all ranks and banks simultaneously. Leveraging its deep on-board memory, the system also offers additional views to help developers optimize physical address utilization and load leveling.

The Kibra 380 provides loss-less capture of address, command and control signals (ADD/CMD/CNTRL). By focusing on state-based capture and excluding the data signals, the system can record over one billion event samples, which is 8x more than the memory depth provided with today's logic analyzer-based solutions.

In addition to timing analysis, the Kibra generates performance metrics that are displayed for read, write and power down operations. Bus metrics are tracked per bank and per DIMM slot to provide insights into overall memory utilization. DDR3 Interposers are included to address RDIMM and UDIMM memory modules. The Kibra 380 can also address multi-channel DDR3 testing by cascading analyzers using the built-in synchronization ports.

Small and portable, the Kibra 380 is controlled using any Windows-based PC and includes the necessary interposer probes capable of monitoring two slots of quad rank DDR3 DIMMs operating to 1600 MT/s. Along with built-in CrossSync ports for performing multi-protocol analysis, the Kibra 380 also features unique, real-time trigger-out for Read / Write operations (WE). Using this dedicated, low latency SMA trigger out signal, the scope can perform signal integrity testing using the DQ/DQS relationships to distinguish Read / Write operations on the bus. The Kibra 380 analyzer will be available in 2nd quarter of 2011.