Test & Measurement

Teledyne LeCroy DDR4 Bus and Timing Analyzer Ships to Early Adopters

19th September 2012
ES Admin
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Teledyne LeCroy has announced it is now shipping the Kibra 480 bus analyser for DDR3 and DDR4 memory test and verification. The system analyses bus traffic while identifying timing violations and displays both commands and errors using a full function waveform viewer. The Kibra 480 platform integrates extensive customer feedback and continues the rapid evolution of Teledyne LeCroy's first generation Kibra 380 DDR bus analyser with innovative new features that help developers verify JEDEC compliance and DDR memory performance.
At Memcon, attendees can visit Cadence at booth 9 and see a live demo of Teledyne LeCroy's Kibra 480 system analysing Cadence DDR4 memory controller and PHY IP along with Micron DDR4 DIMM modules. As a long-time leader in DDR design IP solutions, Cadence's memory validation team is familiar with the test challenges posed by the higher speeds of DDR4 said Marc Greenberg, Director, Product Marketing, SoC Realization Group at Cadence. The Teledyne LeCroy Kibra 480 is already proving to be a valuable addition to our test efforts and should help developers reduce time-to-market when integrating DDR4 within their product designs.

Teledyne LeCroy's Kibra 480 system represents a significant breakthrough in memory controller testing. Central to this new approach is Teledyne LeCroy's proprietary probing technology designed to non-intrusively monitor DDR4's higher transfer speeds, said Michael Romm, vice-president of product development at Teledyne LeCroy's Protocol Solutions Group. Using a custom designed analog front end, the Kibra 480 provides instant signal lock at speeds up to 2400 MT/s. Higher speeds and faster-locking are critical enhancements that enable reliable capture of MRS commands exchanged during the power-on sequence.

With the Kibra 480, signal sampling occurs at the interposer connection to the system-under-test which eliminates time consuming signal calibration and setup required by logic analyser based approaches. Integrating the probe at closer proximity to the signal under test allows capture of a cleaner signal eye. The higher data rates associated with DDR4 exacerbates the probing issues for logic analysers as loading on the data lines may introduce signal integrity problems.

Software enhancements added to the Kibra 480 system include the new Bank State View that allows developers to visualize distribution of I/O operations across all banks. In addition to the ability to capture MRS commands at power on, the Kibra system will adapt on-the-fly to any MRS commands that may change the memory parameters used by the system-under-test. Other enhancements include a new display that shows the last MRS parameters sent to each rank. Support for mirrored UDIMMs, DDR4 Band Groups and the ability to re-analyse any trace on-the-fly are just a few of the enhancements available in the new Kibra 480 platform.

The Kibra system can be configured for DDR3 and the same system can also be extended to address the next generation DDR4 standard by using different interposer probes. Customers can purchase the system with interposer probe sets for DDR3, DDR4 or both.

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