32-Gb/s BERT streamlines R&D testing

The M8062A 32-Gb/s module expands the J-BERT M8020A high-performance BERT with versatile generator and analyser functionality at data rates up to 32.4Gb/s. 

In the past, engineers had to integrate separate instruments to create a solution for characterising multichannel 32Gb/s devices and systems, which impacted measurement repeatability and test setup and reconfiguration time. J‑BERT’s fully integrated capabilities, such as inter symbol interference (ISI) generation, clock data recovery and analyser equalisation greatly improve device characterisation and compliance testing and significantly simplifies test setups. 

At higher data rates, such as 100G, more complex methods are used to mitigate the effects of higher channel loss. Receiver equalisation consisting of CTLE (continuous time linear equalisation) and possibly DFE (decision feedback equalisation) increase the complexity of receiver designs. Verifying these designs requires testing with a variety of channel losses.

The integrated ISI generation allows engineers to test receivers over a range of channel losses without the need to manually reconfigure cables on external ISI channel boards, which improves measurement reliability and repeatability and saves time. 

The analyser equalisation functionality improves measurement accuracy and repeatability at higher data rates by “opening closed eyes” in the looped-back signal from the device under test (DUT) to the BERT error analyser. To measure a bit error ratio correctly, the sampler within the error analyser requires a sufficiently open eye. High input sensitivity in the error analyser isn’t sufficient to overcome closed eyes at high data rates, where there is more eye closure. At higher data rates, these signals can suffer the same degradation as the signal in the test channel. Without proper equalisation, bit error ratio measurements can be confounded by adding errors in the error analyser itself as opposed to the true errors from the DUT.