JTAG/Boundary-scan Past, Present and Future – Part Two

By the mid ‘naughties’ 2000s the market expectation for ease of use in developing JTAG/Boundary-scan testing saw a notable change. While the enthusiastic early adopters of JTAG testing were accepting of systems that required some significant manual input and engineering ability, the later adopters of JTAG testing and programming demanded more automation and increased ease of use in the choice of tools.

ProVision software was one example of the this new ‘second generation’ toolsets that relied less on user intervention and more on re-usable models and model maps to set-up safe test conditions and cluster test opportunities.

Unified environment

ProVision also offered for the first time a unified environment that supported boundary-scan structural testing, cluster testing (memories logic etc..) and programming of CPLD, PROMs , NOR and NAND flash. The modular approach of the system also meant that adding further features via code ‘plug-ins’ would not disrupt the basic architecture of the system.

The first of the plug-ins that would add functionality to ProVision was a facility to test AC coupled LVDS signals, controlled by logic compliant to the newest standard IEEE Std. 1149.6 (those curious about 1149.5 can web-search this system-level JTAG standard which is effectively moribund).

IEEE 1149.6 introduces new instructions in the BSDL model and new logic structures into the compliant parts.

In ‘dot 6’ compliant parts two new instructions can be used to fire a high speed pulse (EXTEST_PULSE) or a series of pulses (EXTEST_TRAIN) across the network being tested. A standard 1149.1 boundary-scan register (output driver) cell has been enhanced to support ‘Dot 6’. To complete the picture however it is necessary to add a complementary receiver circuit that can reconstruct the pulse signal after it has been degraded as it transitions through the AC-coupling.

As the migration from wide parallel busses (e.g. PCI) to high-speed serial (e.g. PCI-express) continues apace then you can expect to see more devices supporting the ‘dot6’ test method. Indeed even some new memories such as Micron’s hybrid memory cube are already equipped with dot6 test features as are many bus bridges from PLX etc. JTAG ProVision was the first tool to provide ATPG and diagnostics capabilities for dot 6 compliant parts in 2007.

Far from making JTAG/boundary-scan an exclusive system for production test engineers or debug access, several new systems emerged in the final years of the 2000s that promoted JTAG/Boundary-scan testing to hardware development engineers.

Aware of the fact that short-run prototypes (A-model) are likely to be more prone to manufacturing faults than those built on an established, process-proven production line, JTAG/Boundary-scan was at last promoted to designers as a tool for board bring-up and validation.

One of the systems that entered this hardware validation market in 2009 was JTAGLive - it included a free ‘downloadable’ point to point interconnect system called Buzz and received 1000s of downloads upon introduction.

For the first time a designer could use a free tool to conduct interconnect tests using an interface/cable that he probably already had (JTAGLive supports Altera and Xilinx hardware as well as its own basic 1 TAP controller).

What’s more users with an appetite for more capability could ‘bolt-on’ options such as a powerful Python-based scripting system and even core emulation modules to enable what is sometimes referred to a ‘processor controlled test’. Tools like JTAGLive continue to fulfil a niche need for ‘stripped-back’ test software that leverages a designer’s intuition and knowledge of the board to devise functional-style tests.

Compatible controller

In 2011 a completely new technique for harnessing the power of JTAG was introduced that allowed it to be applied to designs without prior knowledge of the interconnect data (netlist). Known as AutoBuzz a user could simply connect a compatible controller to the TAP (or TAPs) of the design – that limited amount of knowledge had to be known – which would then detect the number of parts in each scan chain plus their manufacturer code.  

After then assigning BSDL models to the detected parts the user could set AutoBuzz to scan out connections on a known good board. By toggling each driver pin in turn and looking for activity on input pins a basic ‘connectivity signature’ is produced showing the ‘connected’ boundary-scan drive and sense cells. Using a compare mode the system can then assess a faulty board and highlight any disparities in the connectivity signature.

Asynchronous drivers that can interfere with the process can be masked for consistent results.

The next significant update to standards came in 2013 with a sizeable addendum to IEEE 1149.1 – i.e. 1149.1 (2013). This standard came about during a period of intense activity around 2010, with two separate groups proposing similar updates to the existing 1149.1 standard, which was by then 20 years old. As well as 1149.1 2013 there also existed a group working on IEEE 1687.

‘Dynamic ‘ IC infrastructures

Both groups had identified deficiencies in the existing standard and both groups have addressed these through the introduction of more ‘dynamic’ IC infrastructures. In the case of 1149.1 2013 the driver for the changes was to standardise some of the practices that IC vendors had introduced on a unilateral basis, such as initialisation protocols, individual device id codes and power management scenarios.

While in the case of 1687 the main driver was to improve board-level ‘testability’ through the greater use of embedded test cores (BIST IP) accessed via an extended standardised infrastructure.

The now ratified extension to 1149.1 has more than doubled the size of the descriptive document to 444 pages and includes the syntax of a new procedural description language (PDL) that is used to define the usage of the dynamic register segmentation and device IP hierarchy for a given application. IEEE 1687 meanwhile also features PDL, however there is only a basic level of compatibility between the two PDLs – apparently due to the vastly different focus of each new standard !

PDL is designed to document the procedures for stimulating and observing test data register fields for 1149.1-2013 and in P1687, the procedures for stimulating and observing data to an instrument. Not much of a difference except that in P1687 a second language is required to describe the [embedded instrument] access networks – ICL (Instrument Control Language) while in 1149.1-2003 the access network descriptions are embedded in an extended BSDL model. For complex networks that make extensive use of embedded instruments P1687s ICL is claimed to be better suited.

The argument for the continued development of standards is clear. Chiefly these are a) to keep the technology relevant to today’s designs and b) to ease the task of tool vendors who rely on standard techniques to achieve maximum levels of automation in application generation. c) expand the market potential a given methodology.

This is the second part of James Stanbridge’s series on the development of JTAG/Boundary Scan Technology.

The first part was published in Electronic Specifier’s productronica supplement - http://www.electronicspecifier.com/magazine/estandm/productronica-2015-supplement/

The concluding part of the series will be published in the Test & Measurement section of the Electronic Specifier website on December 3.