Interposer solutions enable DDR4 design test on logic analyser

The Agilent W4633A BGA interposer is used with Agilent E5849A probes for high-data-rate DDR4 x4 or x8 DRAM designs. The Agilent W3636A BGA interposer allows engineers to probe DDR3 x16 nonstacked DRAM more than 2 G deep.

As the industry transitions to DDR4 data rates up to 3.2 Gb/s, engineers working on next-generation memory systems – such as those used in servers and embedded devices – face significant challenges. Probing and accurate signal capture are becoming increasingly critical for debug and validation of new designs.

Both interposer solutions provide direct access to the balls of the DDR4 x4 or x8 DRAM with low loading and minimal impact to signal integrity on embedded system design. The probe works in existing designs and eliminates the need for up-front planning or redesign. Both interposer solutions are designed to be used with Agilent’s U4154A logic analyser system, which offers 4Gb/s state speed and 2.5GHz trigger sequence speed.

The W3630 Series DDR3 BGA probes are used with oscilloscopes and logic analysers to perform physical-layer and functional tests for data rates up to 2400 Mb/s with the U4154A logic analysis system.

Features of the Agilent DDR3/4 test solutions include;

• The B4622B DDR2/3/4 and LPDDR/2/3 protocl compliance and analysis toolset, which provides four different software tools: two for functional protocol compliance checks, one automated physical address trigger setup tool, and one tool that provides an overview of system performance through bus statistic information and a histogram view of address access. These tools help reduce memory designers’ troubleshooting time and increase productivity and efficiency in DDR design validation work
• The B4621B DDR2/3/4 protocl decoder software, which translates acquired signals into easily understood bus transactions showing associated data bursts. Valid read and write commands are decoded to include row and column addresses and the complete data burst associated with the command. The B4621B bus decode software anticipates key system attribute inputs from default DDR2, DDR3 or DDR4 probing configurations or the DDR setup assistant tool to accelerate decode of DDR2, DDR3 or DDR4 bus signals
• The DDR eye scan/eye finder, which provides unique eye-scan capability to automatically place the sampling point in both time and voltage within the eye on each individual channel for optimal sampling reliability. The DDR eye-scan display provides bus-level signal integrity insight for a qualitative comparison of all signals scanned under the same conditions
• The DDR setup assistance tool, which guides users through a short series of questions and pull-down menus to assist in tuning state mode measurements on DDR2/3/4/ or LPDDR2/3/4 measurements

The U4154A logic analysis module with 4-Gb/s state speed and 2.5-GHz trigger sequence speed enables full capability so engineers can reliably trigger and capture DDR4 signals at 3.2 Gb/s. When used with the new DDR4 probing solution, the B4621B decoder and B4622B compliance software toolset, this module provides full test capability for system integration in the memory industry