GoldenGate opens way to faster large-signal analysis

Advanced wireless standards such as LTE Advanced (4G) and 802.11ac (WLAN) put high demands on linearity, bandwidth and noise performance, which is changing the nature of transceiver IC design. The new software release introduces verification test benches that allow RFIC designers to easily validate and optimise their designs using standard-compliant waveforms and measurements such as EVM/ACLR in transmitters, or sensitivity/desensitisation in receivers.

With this latest release, a new sensitivity analysis has been added that can be applied when analysing RF circuits, even when running large-signal analyses.

Golden Gate enhancements include the fast circuit envelope (FCE) model export from GoldenGate to SystemVue, which now includes noise support that is critical for any receiver test (e.g., sensitivity/desensitisation). FCE creates a model that is used in SystemVue to represent the degradation due to the RFIC in system-level simulations without facing much of a performance impact.

It also offers fast yield contributor support in envelope transient and S-parameter analyses, which provides a dramatic speed-up of Monte Carlo simulations for process and mismatch variations. It also provides a contributor table to identify root cause devices and/or blocks.

Core solver improvements, such as a new oscillator algorithm, that specifically target high-Q oscillators and high-level transient accuracy control are also included as well as a new automatic steady-state detection and auto-harmonic estimation within initial transient, which reduces simulation time and increases design efficiency.

A broad range of usability enhancements within the graphical user interface, results display and post-processing functionality. Examples include new band spectrum functions for envelope transient measurements or mean value, and standard deviation for each noise source within the noise contribution table.