electronica to host PCI Express BERT extension demo

23rd October 2014

Mick Elliott

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A new option for Bit Error Rate Test (BERT) of PCI Express compatible high-speed bus systems was launched at the International Test Conference in Seattle by Goepel Electronic. The option will also be demonstrated at the upcoming electronica exhibition which takes place in Munich (Nov 11-14).

The highly automated solution enables FPGA Embedded Instruments utilisation in the form of special softcores for the test and design validation of PCI Express x1/x4/x8/x16 interfaces according to PCIe 1.0/2.0/3.0. The therefore necessary instruments are simultaneously configured for each channel. To support the design validation, a graphical evaluation by eye diagram is possible.

Relevant parameters for validation such as pre-emphasis, equalising, etc. are interactively adjustable and become immediately effective without recompiling of the IP. The application can automatically be generated by the Automatic Application Program Generator (AAPG) integrated in SYSTEM CASCON.The Bit Error Rate Test allows the qualitative evaluation of transmission channels and is of utmost importance for PCIe interfaces due to their Gigabit speed.

The use of BGA components increasingly complicates the ability to contact with external instruments and such contact, if even possible, causes undesirable signal distortions. It is the aim of ChipVORX, after chip assembly, to provide design embedded BERT tools for test as well as for hardware validation based on eye diagrams.