Free Keithley Web-Based Seminar Addresses High Voltage Wafer Level Test Techniques

To register for this event, visit http://www.keithley.info/highvoltage.



Many parametric test engineers are learning to cope with new high voltage process requirements. High voltage processes require high voltage parametric testing for process control and reliability monitoring. Part of the challenge is that these new high voltage requirements add to the list of parametric tests rather than replace it. In many if not most cases, the high voltage transistors are controlled by complex logic that requires low voltage/low current parametric test. Consequently, both high voltage and logic level tests need to be realized within the same test plan with a minimum impact on throughput. Automated test equipment configuration and test plan development play a critical role in success.



The seminar will address a variety of topics:



* High voltage probe card requirements

* Hot switching and cable charging risks

* Protecting low voltage instruments during high voltage testing

* High voltage parametric test roadmap



This seminar is recommended for test department engineers and managers in the semiconductor industry who are interested in learning more about the practical issues related to high voltage parametric test and characterization in a production environment.



Paul Meyer, the web seminar presenter, is a senior staff technologist for the Semiconductor Measurements Group at Keithley Instruments, Cleveland, Ohio, which is part of the Tektronix test and measurement portfolio. Prior to joining Keithley, Paul’s career included designing semiconductor fab equipment, as well as equipment and equipment engineering in semiconductor fabs.