GOEPEL electronic upgrades ChipVORX to FPGA Embedded Instruments for Bit Error Rate Tests (BERT)

Users can now evaluate the transmission channel quality via measurement of the bit error rate. A graphical evaluation via eye diagram is possible to support design validation.



ChipVORX takes over the complete process flow starting with Target FPGA programming, IP to pin configuration, instrument control as well as data processing and the final IP unloading. In the debug mode, the BERT parameters can be changed interactively for immediate effect without design synthesis. That makes the utilization of the new BERT solution highly efficient and user-friendly.



“Our announcement on ChipVORX prototype demonstration for Bit Error Rate Tests in November last year generated an enormous interest, which finally reflects this technique‘s strategic importance for quality assurance of modern high-speed designs“ says Thomas Wenzel, GOEPEL electronic’s managing director of the JTAG/Boundary Scan Division. “The new IP provide the frame conditions in terms of access to validate and test embedded designs with FPGA based GBit even more efficient in the future. At the same time, we strengthen our leading position for synthesis-free FPGA Embedded Instruments.”