eBook examines JTAG TAP flaws
Visibility into the operations and data stored on circuit boards and in semiconductors is the goal of test and debug. Unfortunately, this is often at odds with the goals of circuit board security. A new eBook published by ASSET InterTech addresses the inherent weaknesses in the IEEE 1149.1 Boundary-Scan (JTAG) standard’s Test Access Port (TAP) found on many circuit boards and chips.
It and describes several general security strategies based on the IEEE 1687 Internal JTAG (IJTAG) standard that can overcome these problems.
“There is no industry standard for making a circuit board’s test and debug facilities secure,” said Al Crouch, chief technologist, embedded instrumentation methodologies and IJTAG, for ASSET and one of the co-authors of the eBook. “As a result, any board test security is usually derived from the security contained in the chips on a board and each chip has its own security methods. Board-level operations may have some encryption for security purposes, but the TAP still represents a vulnerability that hackers and counterfeiters can exploit unless security measures are designed into the circuit board.”
Titled “JTAG | IJTAG Semiconductor and Board Test Security”, the new eBook is available for free.
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