Clock recovery options boost signal quality analyser

7th May 2014

Mick Elliott

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Datasheet

Anritsu has released new Clock Recovery options for its MP1800A Signal Quality Analyser (SQA), providing for Bit Error Rate (BER) testing of high-speed interconnects at up to 32.1Gbit/s with a single instrument. The latest high-speed serial communications equipment uses components such as SERDES devices, Active Optical Cables (AOC) and optical transceiver modules, which send and receive serial data without transmitting synchronous clock signals.

Previously, BER and jitter tolerance measurements of these systems required an external clock recovery instrument. With the introduction of the internal Clock Recovery options for the MP1800A, users can perform these measurements with a single box. The MP1800A is a modular-type BERT composed of a Pulse Pattern Generator (PPG), plus a high input-sensitivity Error Detector (ED).

A jitter modulation source may be installed in the instrument to generate various types of jitter, enabling users to test a device’s jitter tolerance. BERT testing is widely used by manufacturers developing new generations of network equipment designed to handle the rising volumes of data traffic worldwide. To increase processing speeds, high-performance servers in data centers are standardising on high-speed serial communications methods exceeding today’s 25Gbit/s data rates, such as 100GbE (100G Base CR4, KR4), InfiniBand EDR, CEI-28G, 32G FC and others.

Trunk communications networks are developing next-generation transmission technologies supporting data rates of 400Gbit/s.

Installing the new Clock Recovery options announced today strengthens its capabilities, providing for clock-less device BER measurements and jitter tolerance measurements, and leading to more accurate signal-integrity analyses across a wide range of applications.