Agilent Technologies Offers Simplified Receiver Tolerance Test Setup for USB 3.0, SATA and SAS

The J-BERT's second output channel option provides more flexible characterization and compliance testing of receivers by enabling cross-talk testing, Out-of-Band (OOB) tests, and emulation of 2-tap de-emphasis signals on a serial BERT.

The new symbol error analysis option allows error counting of coded, packetized and retimed data streams. This significantly simplifies jitter tolerance testing of devices, using retimed loopback modes, such as SATA, USB 3.0, SAS, and MIPI M-Phy.

USB 3.0 and SATA are popular examples of digital interfaces using 8B/10B coded and packetized data streams with retimed loopback. These digital interfaces require special test capabilities for the characterization and compliance testing of receivers.

Coding is used to limit the number of consecutive 0s or 1s in transmitted bit streams. Running disparity is used to achieve DC balance. The transmitter and receiver on both ends of the link are clocked with independent reference clocks. Differences in the reference clocks are compensated by inserting or deleting filler symbols, such as ALIGN or SKIP symbols.

During receiver tolerance testing, the device under test (DUT) operates in a retimed loopback mode. This means that the bit stream received by the BERT analyzer can be different in data rate and bit pattern from what the BERT generator sent out, even if no receive error occurred. This behavior is challenging for traditional bit error ratio testers that expect a predictable pattern to compare with the actually received bits. Receiver tolerance testing required either external error-counting equipment or a BERT, which had pattern capture mode to retrieve the error ratio from a DUT's built-in error counter.

This is a significant milestone in adapting the industry's leading receiver tolerance test solution to the latest requirements, said J�rgen Beck, general manager of Agilent's Digital Photonic Test product line. Receiver tolerance testing is considerably simplified with the second data channel option and the symbol error analysis option for J-BERT. Once again, we prove our commitment to enable R&D teams to release the next generation of robust high-speed digital interfaces for the computer, consumer and storage industries.