Image sensor interface features FPGA's from Xilinx

Based on the long term partnership with Sony and as official Xilinx partner, the FRAMOS IP product provides the technological basis for future camera developments and Embedded Vision devices.

Introduced with the third generation Pregius imagers, SONY's new high speed interface standard SLVS-EC is one of the future image sensor interface benchmarks with up to eight lanes providing 2.3Gbps each, for three to four times higher bandwidths, higher resolutions or a simplified system design comparing to SubLVDS.

The FRAMOS developed RX IP Core reduces overhead and complexity implementing a SONY imager with SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock). As on-chip function block connecting the customer's FPGA logic with the image sensor's data stream, the IP Core receives the interface data, manages the byte-to-pixel conversion for various lane configurations and thus prepares a highly efficient processing workflow run by the FPGA.

The FRAMOS software will support SLVS-EC v1.2 with 1, 2, 4, or 8 lanes configurable by the user and delivers pixels formats from 8 to 14bit of raw data. By de-risking the sensor implementation it significantly reduces the development efforts and accelerates the time to market. Partnering with FRAMOS, customers can maximise their strength in innovation by focusing on core competencies.

Simon Che'Rose, Head of Development at FRAMOS explained the advantages for system designers: "SLVS-EC is the benchmark interface standard of the future for high speed data transfer from SONY imagers. It uplifts existing and upcoming CMOS designs to the next speed and performance level and supports miniaturisation.

"Each customer using SONY image sensors either working with high speed or embedded solutions will benefit from the SLVS-EC interface and its unique features. Our RX IP Core Block for Xilinx FPGAs in combination with the full documented evaluation kit makes integration and system development easy, resulting in a faster time to market for customer applications working with SLVS-EC."

The FRAMOS SLVS-EC RX IP core is the first solution for Xilinx FPGAs on the market. As an official Xilinx partner, FRAMOS is working in close cooperation with Xilinx. The SLVS-EC RX IP Core will work with the main existing and upcoming FPGA families. The package includes the encrypted RTL IP Core with a simulation environment (ModelSim) and dedicated reference implementation examples and supports customers to get up to speed based on FRAMOS' 37 years imaging experience.

The available EVB will provide designs to guide and test the implementation of a SLVS-EC-based sensor, including the HW/SW environment and documented implementation examples with sources. With SLVS-EC, users can benefit from faster sensors with an increased performance, and from a simplified and smaller hardware design by using less lanes.

With the Embedded Clock, the interface is robust against clock-skew, allowing larger bandwidth and making dedicated clock lanes obsolete. In industrial applications, FPGAs are a common way to manage sensor control and timing, perform image pre-processing and transform data to common interfaces. SLVS-EC and FPGAs are key to Embedded Vision development and allow high bandwidth and massive parallel processing capabilities while being flexible and efficient.

The industry and product experts at FRAMOS have applied their profound knowledge of sensor technology to support customers integrating the new sensors with the SLVS-EC interface standard into their applications and projects, together with additional services like development support, customisations, and logistics. The SLVS-EC RX IP Core will be released mid-May, 2018.