FRAMOS completes IP Core for sensor integration

The IP Core comes as an encrypted file. A reference design implementation with a sensor module kit and everything developers need for testing and implementation purposes is also available.

The IP Core is available for AMD/Xilinx platforms such as the UltraScale+, the Kintex series, and many more. Installing the IP Core enables the new SLVS EC v3 interface to be used, which leads to high bandwidths for data transmission between the sensor and the FPGA. This is particularly useful for customers who want to achieve razor-sharp image results for their vision applications, such as those required for medical imaging, sports events, or fast industrial applications.

Using the SLVS EC RX IP core drastically reduces the integration time for camera and imaging systems, thereby reducing the risks involved in project implementation. SLVS EC v3 enables a data transfer rate that is twice as high as that of its predecessor standard SLVS EC v2. Transfer rates of up to 10 Gbit/s are possible per data lane in version 3.0. Up to eight lanes can be used on the developer board side and pixel formats up to 16 bits are supported. This enables future imaging processes with already existing and upcoming high-resolution image sensors compatible with SLVS-EC v3.

“SLVS EC v3 and higher enables high data transfer rates, as required by upcoming, high bandwidth requiring and already available top-of-the-range sensors. Our IP core makes the future tangible here through its ease of use, allowing vision system developers to forget complexities of the image sensor interface and focus on what is important: the application,” said Giuseppe Contini, Technical Imaging Expert, FRAMOS.