Understand your FPGA’s power rails

9th August 2012

ES Admin

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Modern PLDs have a core supply rail that powers most of the device and consumes the highest power. With every new technology node, there is a new core supply voltage rail. Auxiliary voltage-supply rails power supporting circuits such as configuration logic, clock managers, and other housekeeping circuits.

In addition, FPGAs are typically used to bridge one interface standard to another and each I/O driver has its unique voltage rail ranging from 1.2V to 3.3V. Example interfaces include LVTTL/LVCMOS, LVDS, bus LVDS, mini-LVDS, HSTL, SSTL, and TMDS.

Special care is needed in powering high-speed SerDes transceivers, each of which can consume 1A to several amperes of current and run at speeds of 155Mbit/s to 28Gbit/s and beyond. A 100G Ethernet application, for example, uses many such transceivers and consumes 10A or more of current. Because of the high speeds involved, a noisy power rail is particularly detrimental to their performance.

There are three steps to take to determine your FPGA’s power needs:
-Determine the input voltage. You can use the FPGA data sheet’s power estimation for this. Make sure to identify all the required voltage rails and currents;
-Refer to the data sheets for the possible power regulators. Determine that the specifications for VIN, VOUT, IOUT, sequencing, interfaces, and programmability meet the requirements of the FPGA;
-Use a manufacturer’s product database to sort and select the best part for the FPGA and application.

If this abstract has piqued your interest, read the full article online in the August issue of Electronic Specifier Design, by clicking here.