Integrated Li-Ion battery linear charger with power routing switch and parallel power paths for portable applications

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br />1 Introduction

##IMAGE_1_R##Portable devices become more widespread every day. Each of them requires a rechargeable energy storage device for its operation. The most appropriate storage device for portable applications today is the Li-ion battery – single- or multicell. As this battery is rechargeable every portable device needs a battery charger integrated circuit (IC). Due to the large charging currents, the battery charger occupies a significantly large area. However, the trend in microelectronics is minimization of the area. Thus the battery charger integrated circuit has to be as small as possible.

The battery charger described in this paper uses a parallel power path structure, which allows the reduction of its area compared to conventional linear battery chargers with a series power path with the same power dissipation.

The speed of the Li-ion battery charging is also important. To make the charging process faster it is necessary to distribute current between the battery and internal system of a portable device as efficiently as possible. In the architecture described we use adaptive current sharing circuitry. This allows increased battery charging current when the portable device current demand drops. In addition we increase battery usage efficiency by implementing the power routing switch. This switch isolates the battery from the system whilst a wall adapter is plugged in.

The proposed architecture also provides measurements of the charging/discharging currents with relatively high accuracy. This data can be used for fuel gauging. As a result the proposed architecture of the linear battery charger occupies less area and provides more effective battery charging.

2 Proposed battery charger description

2.1 Parallel power path

Conventional linear battery chargers use a series power path architecture as shown in Fig. 1a and described in (1), (2), (3). Though this approach requires the same number of power MOSFETs the occupied area is larger than in the case of a parallel power path structure, Fig. 1b. In linear chargers, power MOSFETs operate in the linear region during constant current mode. Drain-source current of a MOS transistor operating in the linear region can be presented as
    [1]
where V_gs is gate-source voltage of MOSFET, V_T is threshold voltage of MOSFET, V_ds is drain-source voltage of MOSFET and ß can be presented as
    [2]
where W is the channel width of MOSFET, L is the channel length of MOSFET, µ is mobility in the channel and C_ox can be presented as
   [3]
here _e is the permittivity of silicon, _e0 is the permittivity of vacuum and D is oxide thickness.

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Fig.1. Power flow diagram of (a) series power path structure and (b) parallel power path structure

Power transistor minimum size is limited by its minimum value of drain-source voltage V_ds which allows a transistor to operate in the linear region at maximum drain-source current I_ds. In a series supply path structure, Fig. 1a, maximum I_ds of the power FET Mps1 is determined by maximum input current from AC adapter i_ds,mps1=I_IN. In turn maximum input current is the sum of maximum battery charging current and maximum system load current i_in=I_SYS + I_CHG. The system voltage V_SYS in a series power paths structure is always higher than battery voltage by voltage drop across Mps2. The system voltage reaches its maximum value when battery voltage is equal to battery termination voltage v_sys=V_TERM + V_ds,Mps2. Minimum drain-source voltage across Mps1 is v_ds,mps1=V_DC - V_SYS. Using [1] - [3], the minimum necessary Mps1 size is
    [4]
The second power FET Mps2 operates with maximum drain-source current, which is equal to maximum battery charging current i_ds,mps2=I_CHG. Minimum voltage drop across Mps2 is v_ds,mps2=V_SYS - V_TERM. Thus minimum necessary size of Mps2 is
   [5]



In a parallel power paths structure maximum I_ds of Mpp1, Fig. 1b, is determined by maximum system load current i_ds=I_SYS. Minimum V_ds is defined by system voltage V_SYS and can be presented as v_ds=V_DC - V_SYS. This approach allows the system to be independent of battery voltage unlike in a series power path structure. Using [5] the minimum necessary size of Mpp1 is
    [6]
For Mpp2 maximum drain-source current is i_ds=I_CHG and minimum v_ds=V_DC - V_TERM. Thus the minimum necessary size of Mpp2 is
    [7]

Equations [4] - [7] show that the two power FETs of the parallel structure require less area than Mps1 of the series structure. In addition Mps2 is larger than Mps1. However, in a parallel battery charger there is no connection between battery and system. But when the charger is off, the system should be supplied from the battery. This is the reason for using the power routing switch shown in Fig. 2. This transistor is not involved in the battery charging process and acts as a switch for isolating the battery from the system. Where a battery is fully charged and the AC adapter is still plugged in, all the power comes from the wall adapter and the battery is protected from unnecessary charging/discharging cycles. In order to decrease power dissipation across the power routing switch during battery discharging its on resistance should be minimised. In the series linear chargers transistor Mps2 acts as a power routing switch in the linear structure. To be precise in comparison of the two architectures we assume that power dissipation across the switch during discharge is the same and thus Mps2 and the power routing switch require the same silicon area.

Nevertheless the parallel structure is still more area effective due to the smaller total size of Mpp1 and Mpp2 compared to Mps1. Also independent and constant system voltage might be considered as a benefit.

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Fig.2. Power routing switch in parallel power path structure

2.2 Battery charging circuitry

The first of the two parallel power paths of the proposed linear charger architecture acts as battery charging circuitry. Linear battery chargers have three operating modes: constant current (CC), constant voltage (CV) and temperature regulation, which protect the circuit from overheating (4). Sequential regulation loops are built using three open drain error amplifiers with outputs connected together that perform the majority analog function of three input control signals (5). Fig.3 shows basic operation of the proposed battery charging circuitry. CC error amplifier drives a power MOSFET when the selected charging current is flowing through a power transistor. CV error amplifier drives a power MOSFET when the battery voltage reaches the selected termination voltage. The temperature amplifier operates when temperature reaches the maximum allowed regulation temperature, which is measured by a temperature sensor. In this case charging current decreases smoothly until the temperature drops.

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Fig.3. Block diagram of proposed battery charging circuitry

Often linear battery chargers use a PMOS transistor as power FET (6), (7), (8). Its size is determined by drain-source voltage drop at the maximum charging current or, in other words, by drain-source resistance R_ds. However NMOS R_ds is smaller compared to PMOS of the same size due to the larger mobility of the carriers. In order to minimize battery charging circuitry area we use NMOS for the power FET. It is regulated with a simple charge pump whose output voltage is large enough to drive the power FET up to maximum battery voltage.

2.3 System low dropout regulator circuitry

The second power path operates as a low dropout regulator with accurate current limiter. Requirements for current limiter accuracy are higher as in conventional LDOs. Excessive current can damage not only the external system but also an AC wall adapter.

In order to increase current limiter accuracy, we implemented an additional error amplifier, which drives the power FET of the system LDO during overload (Fig.4). Note that the principal operation of two error amplifiers and implementation of an NMOS transistor as power FET in system LDO is similar to the approach implemented in battery charging circuitry.

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Fig.4. Block diagram of proposed system LDO circuitry

The simplest current limiter realization in LDOs is performed by mirroring the power FET with a sense transistor. To achieve an accurate ratio of drain-source current between the power and sense FETs gates, drain and source voltages should be equal. However, in case of the NMOS power FET drain-source current ratio accuracy is less compared to the PMOS power FET due to the quadratic relationship between drain-source current and gate-source voltage.

To minimize inaccuracy between drain-source currents of the power FET M_P and sense FET M_S, we implemented an additional current amplifier for creating equal source voltages. The major effect on current limiter accuracy comes from the mismatch of M_P and M_S. It can be reduced by introducing trimming of the sense current. Transistor M_trim is selectable and it regulates current through M1. This current is directed into the resistor R1, which is connected to ground. An obtained voltage is proportional to current flowing through the system LDO and is fed back into the current limiter amplifier. This amplifier drives the power MOSFET when system current exceeds the selected current limit value.

2.4 Adaptive current sharing circuitry

Battery chargers should not only protect a battery but also the AC wall adapter. Because of the parallel power path structure it is possible to overload a wall adapter very easily. Total input current flowing from the adapter is the sum of battery charging current and system load current i_in=I_SYS + I_CHG. By choosing appropriate battery charging current I_CHG is limited. I_SYS can be limited by the system LDO current limiter. Current demand of the external system varies in a relatively large range depending on its operating mode and is unpredictable for the battery charger. In this case it is possible to limit battery charging current at the level of fullrate constant current and system current at the level of I_IN-I_CHG, but this will limit the operation of the external system.

To increase the efficiency of the battery charging we implemented adaptive current sharing circuitry. It allows the battery charging current to be reduced smoothly while the load is increasing and the wall adapter will not be overloaded. Fig.5 shows detailed implementation of this approach.

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Fig.5. Block diagram of the adaptive current sharing circuitry

Current flowing through the charger and system LDO power MOSFETs Mp_sys and Mp_batt is mirrored by sense transistors Ms_sys and Ms_batt respectively. Sense currents are transformed into feedback voltages of the current limiter amplifier of the system LDO and CC mode error amplifier of the battery charger by resistors R0 and R1. These two operational amplifiers drive power FETs depending on feedback voltage. Reference voltages are created in the VREF block and are selectable by user. Reference voltage for adaptive current sharing circuitry is the difference between the reference voltage of the current limit amplifier and reference voltage of the CC mode error amplifier V_{REF_curlim} - V_{REF_ibatt}. Adaptive current sharing amplifier output is high until the feedback voltage of the current limiter amplifier, which is proportional to system load current, exceeds the reference voltage of the current sharing circuitry V_{REF_share}. Then the current sharing amplifier starts to regulate transistors M1 and M2. Current flowing through M2 is directed to resistor R1. This additional current increases the feedback voltage of CC mode error amplifier which, in turn, reduces the battery charging current smoothly.

2.5 Charging and discharging current measurement circuitry

Most of the smartphones available on the market use fuel gauging for determination of battery state of charge and state of health. This function requires accurate charging and discharging current measurements. The proposed architecture allows the measurement of charging and discharging currents with sufficient accuracy in two ways. First, using an external sense resistor and secondly, using a power routing switch.

Fig. 6a shows a simplified block diagram of charging/discharging current measurement circuitry using an external resistor. An external resistor is preferable to an internal resistor due to its superior accuracy over temperature range. The main principle of this approach is to tap a small part of the current flowing through the external resistor with resistor R0 and measure this current. Measurement is performed with help of a chopper amplifier whose offset voltage is small and its impact on total current measurement accuracy is reduced. Resistor R1 creates a voltage proportional to charging/discharging current. The disadvantage of this method is an additional external element that occupies printed circuit board (PCB) area and increases total cost.

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Fig. 6. Charging/discharging current measurement using (a) external sense resistor and (b) power routing switch

To provide more options we implemented circuitry that allows measurement of the current flowing through the power routing switch. The simplified block diagram is shown in Fig.6b. Its operational principle is the same as for the external sense resistor. The difference is in compensation elements. In this case a small current is tapped by the PMOS FET the I/V dependence of which is similar to the power routing switch. However, due to the small channel resistance of the power routing switch parasitic resistance caused by metal contacts from drain and source to package bumps or pads increase actual resistance comparing to simulations. This parasitic part of the total resistance is compensated by metal resistor R0. Otherwise it would affect the charging/discharging current measurement accuracy.

3 Measurement results

The linear parallel power path battery charger was fabricated in a 0.18μm CMOS process using 5V and 28V voltage domains. The active chip area is 1.4mm² (Fig. 7). 28V NMOS used as power FET Mpp1 occupies 0.25mm² with measured Ron of 360mOhm. 28V NMOS used as power FET Mpp2 occupies 0.2mm² with measured Ron of 460mOhm. 5V PMOS used as power routing switch occupies 0.3mm² with Ron of 61mOhm.

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Fig.7. Layout of the implemented battery charger

Fig. 8 shows measured battery charging accuracy of ±2% and system LDO current limiter accuracy of +10%/-1% at the current range of 50…1200mA after trimming at room temperature. Samples have been trimmed at 750mA current. At this value the accuracy is ±2% in temperature range of -40°C…125°C.

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Fig.8. Battery charging current accuracy

Current sharing operation has been checked for different values of system LDO current limiter and battery charging current. Fig. 9 shows the battery charging current/input current profile at 1200mA system LDO current limiter and 1150mA battery charging current versus external load current. As a result, the battery charging current drops with increase of load current in a way that means input current does not exceed the allowed value. The accuracy of the input current during current sharing operation is ±2.5% over -40°C…125°C temperature range.

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Fig.9. Current sharing operation

The current measurement circuitry uses a compensation metal resistor, which represents the resistance of the metal contacts and bumps. Simulation results in Fig.10 b) show that this compensation creates significant error of current measurement compared to Fig.10 a) where a compensation resistor is not included. However, the measurement results in Fig.11 show that current measurement accuracy is high and thus the compensation element has been estimated correctly. The accuracy of battery discharging current measurement is +6/-3%. The summary of the characterization results are presented in Table I.

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Fig.10. Discharge current measurement through power routing switch a) without compensation metal resistor and b) with compensation metal resistor

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Fig.11. Discharge current measurement through power routing switch

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Table1. Summary of LDO’s main parameters

4 Conclusion

The presented work had the aim of creating a Li-ion battery linear charger that occupies less silicon area than conventional linear battery chargers with the same power dissipation. Another requirement was to increase battery charging/discharging efficiency. In order to achieve these goals we used different design approaches. The area reduction has been achieved by using a parallel power path structure with NMOS power FETs. A power routing switch and adaptive current sharing circuitry improve the efficiency of the battery charging and discharging process. In addition, the proposed charging/discharging current measurement circuitry – which has relatively high accuracy - allows the use of this battery charger in conjunction with an external fuel gauging system. Such a combination may improve battery management of a portable device.

References

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