SiC FET lowers conduction losses

In almost every attribute SiC MOSFETs are better than Silicon MOSFETs. One part where they are worse is the MOS channel resistance, which can largely contribute to die size and is much bigger than in Si MOSFETs.

Most vendors for SiC FETs offer just such “normal” SiC MOSFETs, with this disadvantage.

JFETs instead don’t have this channel resistance nd can therefore offer much smaller on-resistance for same die size or smaller die size for same on-resistance. One negative point of JFETs is that they are normally-on devices. In most applications this is not wanted.

To overcome this negative point a cascode consisting of a SiC JFET and Si MOSFET can be used. This results in a normally-off device with all of the advantages of a SiC JFET.

Qorvo’s SiC FETs offer such SiC JFET + Si MOSFET cascode in a single package.

Due to the cascode configuration Qorvo SiC FETs offer many advantages.

For the same chip size Qorvo SiC JFETs offer much better R_DS,On compared to standard SiC MOSFETs both at 650V and 1200V. In fact, Qorvo offers lowest R_DS,ON for SiC devices in the industry which leads to lowest conduction losses.

For the same R_DS,ON on the other hand they enable smaller chip size which leads more chips per Wafer and lower parasitic device capacitances. Lower parasitic capacitances however lead to low C_oss losses and fast ZVS voltage transitions in soft switching applications.

Another big advantage of this configuration is the ability to use standard Si MOSFET gate drivers for driving Qorvo’s SiC FETs as V_GS can go as low as -20V and as high as 20V. This again makes it also compatible with IGBT and SiC MOSFET designs.

Qorvo’s SiC FETs are in general pin compatible to other solutions in the same package but not necessarily drop in compatible. Qorvo’s SiC devices are very fast switching devices with excellent body diode characteristics. That means the operating di/dts value can be very high.

In most cases therefore it will be necessary or at least recommended to add an RC snubber to tune the switching performance and handle these high di/dts, especially when using standard 3-terminal packages.

These snubbers can help to reduce voltage overshoots, suppressing gate oscillations and improving EMI. If no RC snubber would be used it would be necessary to apply higher value external gate resistors to slow down the SiC device to avoid V_DS spikes and ringing during the turn-off transients.

This would have the effect of higher overall switching losses. In fact, Qorvo shows with Double Pulse Tests that even small snubber components lead to much better performance, meaning lower switching losses than slow down SiC devices with higher gate resistor values. These improvements are valid for both, hard and soft switching applications.