Package design enlarges PCB connection
A flip-chip package design, developed by Alpha and Omega Semiconductor meets telecommunications' requirements for secondary rectification and where parallel operation is critical.
The AOE66410 combines Source Down packaging technology with AlphaSGT, the company's shield gate technolgy, to produce a 5.0 x 6.0mm DFN package. The 40V flip-chip device is particularly suitable for telecommunications applications for secondary rectification, in half bridge configuration for brushless DC (BLDC) motor applications and battery management where paralleling is important.
It has the same form factor as a standard DFN 5x6 package but the source pad has the largest connection to the PCB, says the company. This will enable power supply designers to parallel devices more easily and have a larger thermal area to dissipate any losses. It has 1mΩ max at 10Vgs and a maximum drain current of 100A at 25°C case temperature.
The AOE66410 is available in production quantities with a lead time of 12-14 weeks.
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