Measuring and evaluating PSRR in low dropout regulators

Introduction to Low Dropout Voltage regulators (LDOs) and their critical role in maintaining a stable output voltage

This article explores the challenges of using LDOs to maintain a stable output voltage and provides insights into optimising LDO performance. We delve into the intricacies of PSRR, noise in LDOs, and the critical conditions to acquire accurate PSRR measurements. Furthermore, we investigate the requirements for using output capacitors with low parasitic parameters to enhance LDO stability and efficiency. The use of capacitors with low Equivalent Series Inductance (ESL) and low Equivalent Series Resistance (ESR) is dissected in detail.

In the quest for high efficiency, we explore strategies to minimise voltage drop across the LDO (V_DROP), and consider power sequencing techniques to reduce working time, especially in applications with limited power availability.

Through practical considerations, real-world examples, and case studies, we aim to provide actionable insights for engineers and designers seeking to optimise LDO performance. The following sections will describe these topics, offering a comprehensive guide to understanding and addressing the intricacies of LDOs in electronic systems.

LDOs are particularly valued in applications where power efficiency and space are critical, such as in battery-powered devices, portable electronics, and sensitive analog circuits. Their simplicity, low noise, and ability to regulate voltage close to the input level make them indispensable in situations where a stable and clean voltage supply is needed.

Challenges in LDO design

Designing an efficient LDO regulator comes with several challenges, particularly regarding Power Supply Rejection Ratio (PSRR) as well as noise.

Power Supply Rejection Ratio (PSRR)

PSRR is a measure of how well the LDO can suppress variations (or noise) from the input power supply. High PSRR is crucial for ensuring that fluctuations in the input voltage do not affect the stability of the output voltage. However, achieving high PSRR (especially at high frequencies) can be difficult and often requires careful design of the feedback loop, error amplifier, and pass element.

Noise

Noise generated within the LDO itself can also degrade the performance of sensitive analog or RF circuits. Minimising output noise while maintaining regulation accuracy and efficiency is a common challenge, particularly in low-power or low-dropout scenarios.

These two factors make LDO design a balancing act between stability, efficiency, noise performance, and the specific needs of the application.

LDO PSRR and noise explained

Understanding PSRR (Power Supply Rejection Ratio)

As previously mentioned, Power Supply Rejection Ratio (PSRR) is a critical metric that gauges how well an LDO can maintain a stable output voltage in the presence of varying input power supply conditions. High PSRR is particularly essential in applications where the input power supply is subject to fluctuations, ensuring the reliability of the supplied voltage. Figure 1 below shows the principle behind measuring PSRR.

Figure 1: Measuring PSRR

PSRR is calculated using the following equation:

Figure 2: LDO PSRR (dB) vs. Frequency (Hz)

Factors influencing PSRR

Several factors can influence PSRR, making accurate measurements and considerations vital for effective LDO design:

1. Input frequency range

The PSRR of an LDO typically varies across different frequencies. It tends to be higher at lower frequencies but degrades as frequency increases.

Guidelines for selection:

■    Test the LDO over a wide range of frequencies, particularly those relevant to the application, such as power supply switching frequencies, harmonics, and noise sources

■    Ensure that both low and high frequencies are covered. Low frequencies are usually dominated by the LDO's error amplifier, while higher frequencies are typically influenced by parasitic elements and circuit layout

2. Voltage variation

Variations in input voltage, particularly ripple voltage or noise superimposed on the DC input, are used to assess the PSRR.

Guidelines for voltage variation:

■    Use voltage ripple amplitudes representative of real-world operating conditions

■    For LDOs in sensitive applications, small ripple voltages might suffice, while LDOs designed for high-noise environments might need larger ripple voltage to test the upper limits of rejection

3. Load conditions

Load conditions can dramatically influence PSRR, as LDOs perform differently under varying current.

Guidelines for load conditions:

■    Measure PSRR under different load currents, ranging from low load (10 mA for example) to full load

■    LDOs often show lower PSRR under heavy load conditions due to increased output impedance and limitations of internal regulation

Effect of load conditions on PSRR:

■    At low loads, the error amplifier in the LDO operates with ample bandwidth, resulting in better PSRR performance

■    At higher loads, due to the increased output current affecting the loop stability and bandwidth of the LDO, it may reduce the LDO’s ability to reject input noise, leading to a lower PSRR

■    It is essential to test PSRR across various load conditions to capture a complete picture of an LDO’s performance

Practical tips for PSRR measurements:

■    Use a high-quality power supply and low-noise signal generator to apply the input ripple or noise

■    Ensure that the measurement setup, including cables and connectors, does not introduce additional noise that could affect the accuracy of PSRR readings

■    Consider temperature variations during testing, as thermal effects may alter PSRR performance, especially at higher load currents

Noise in LDOs

This section delves into the identification of different noise sources and examines their impact on LDO operation. Understanding the nature of noise is fundamental to implementing strategies to mitigate its effects.

Figure 3: LDO Output Noise (μV/√Hz) vs. Frequency (Hz)

Identification of noise sources and a detailed examination of their impact on LDO operation

Identification of noise sources in LDOs:

■    Thermal noise: generated by the random motion of charge carriers (usually electrons) within the LDO's semiconductor material. Thermal noise is broadband and exists across the entire frequency range

■    Flicker noise (1/f Noise): dominates at low frequencies (below 1kHz) and is caused by fluctuations in the carrier density and mobility within the semiconductor material

■    Power supply ripple: any AC components present on the input power supply will translate to output noise if the LDO's PSRR is insufficient

■    Load-induced noise: variations in current load can induce noise at the LDO output, especially if the load changes rapidly or drastically

Impact of noise on LDO operation:

■    Noise present in an LDO can degrade the performance of circuit capabilities, particularly in sensitive applications such as RF communication, analog signal processing, and precision sensors. It can materialise as glitches, jitter, or distortion in these circuits, leading to suboptimal or even faulty performance

Differentiation between various types of noise and their effects on the output voltage

■    Broadband noise: covers a wide frequency range and can be a result of thermal noise and other high-frequency interference

■    Low-frequency noise: often dominated by flicker noise, this type of noise is particularly problematic for circuits that require stability and precision over long periods

■    High-frequency noise: typically stems from external interference or power supply ripple. This noise can be filtered out by choosing appropriate capacitors in the LDO design

Choosing the correct conditions for PSRR measurements

To accurately evaluate the Power Supply Rejection Ratio (PSRR) of Low Dropout Regulators (LDOs), it is crucial to carefully select the measurement conditions. These conditions, such as input frequency range, voltage variations, and load conditions, significantly influence the accuracy and reliability of PSRR measurements. Accurate PSRR measurements are essential for:

■    Assessing LDO performance: High PSRR indicates that the LDO is effectively attenuating input noise, resulting in a cleaner, more stable output

■    Design optimisation: PSRR data helps designers choose the right LDO for applications where power integrity is critical, such as in noise-sensitive analog circuits or RF systems

■    System reliability: understanding the LDO’s PSRR behavior ensures reliable performance, especially under varying operating conditions

In real-world scenarios, electronic systems often operate in dynamic environments where the power supply conditions can vary. Accurate PSRR measurements enable engineers to assess how well an LDO can handle these variations, ensuring the stability and reliability of the entire system.

Requirements for using capacitors with low parasitic parameters

Capacitors are fundamental components in electronics, playing a critical role in stabilising circuits and filtering noise. When choosing capacitors, low parasitic parameters such as Equivalent Series Inductance (ESL) and Equivalent Series Resistance (ESR) are essential for high-performance applications, including Low Dropout Regulators (LDOs). This chapter focuses on capacitors with low ESL and ESR, explaining their significance, selection criteria, and practical considerations for implementation.

Low ESL capacitors

Significance of low Equivalent Series Inductance (ESL)

ESL corresponds to the inductive behaviour of a capacitor, which can degrade performance in high-frequency applications. Capacitors with low ESL provide enhanced noise filtering and stability, especially in circuits such as LDOs where noise rejection is critical. It reduces the phase shift in the feedback loop and suppresses high-frequency noise leading to improved stability and performance. It also prevents oscillations and maintains smooth voltage regulation under varying load conditions, which is vital for sensitive electronics.

Criteria for selecting capacitors with low ESL

Low ESL capacitors minimise the formation of resonances within the circuit, which can lead to spikes in voltage noise. By reducing the capacitor inductance, high-frequency noise is filtered out. Additionally, low ESL capacitors stabilise the feedback loop in LDOs, improving phase margin and ensuring reliable operation across a wide range of loads. Capacitors with low ESL are generally characterised by their construction and material composition. Ceramic capacitors, particularly Multilayer Ceramic Capacitors (MLCCs), commonly have low ESL properties. During capacitor selection, the following criteria should be considered:

■    Type: MLCCs typically offer the lowest ESL

■    Capacitance value: higher capacitance values in small package sizes often indicate lower ESL

■    Package size: shorter lead lengths of smaller packages (e.g., 0402, 0603) tend to have lower inductance

■    Mounting technology: surface-mount capacitors have lower inductance compared to through-hole types

■    X5R or X7R dielectric types of capacitors are suitable for higher capacitance applications

Guidelines for selection should focus on balancing capacitance, voltage rating, and ESL to match the specific frequency and stability requirements of the circuit.

Practical considerations for implementation

■    PCB placement: capacitors with low ESL should be placed as close as possible to the load components or power input to minimise the inductive path. This also helps to achieve better noise filtering and stability

■    Proximity to load: the closer the capacitor is to the load, the more effective it will be in reducing noise and stabilising the voltage

■    Manufacturer guidelines: always adhere to the manufacturer’s recommendations regarding placement, handling, and operating conditions to ensure optimal performance

■    Via design: if vias are required for connection, minimising their number and ensuring proper design can help maintain low inductance

Low ESR capacitors

Significance of low Equivalent Series Resistance (ESR)

Equivalent Series Resistance (ESR) is the resistive element within a capacitor that causes power dissipation. Low ESR is critical in power-sensitive applications, such as LDOs, as it minimises energy loss and improves efficiency. Capacitors with low ESR are more effective at stabilising the output voltage and reducing ripple, especially under dynamic load conditions. They also enhance the transient response, allowing the regulator to quickly compensate for sudden changes in load demand.

Criteria for selecting capacitors with low ESR

When selecting capacitors with low ESR, the following factors should be considered:

■    Capacitor type: ceramic capacitors, especially MLCCs, are known for their inherently low ESR, making them ideal for high-frequency and low-noise applications. Tantalum and polymer capacitors also offer low ESR, particularly at higher capacitance values

■    Temperature stability: capacitors with stable ESR over a wide temperature range are preferable for applications that experience fluctuating operating temperatures

■    Frequency range: the ESR of a capacitor can vary with frequency. Choosing a capacitor that maintains low ESR across the required frequency spectrum is crucial for consistent performance

Practical application and case studies in real-life capacitor usage with high performance SLG51003 Power GreenPAK IC

Measuring the impact of various capacitors on PSRR performance

In practical applications, the Power Supply Rejection Ratio (PSRR) is a key parameter to analyse the performance of capacitors in conjunction with high-performance PMICs. The effectiveness of using specific capacitors to achieve high PSRR performance are shown the following Tables and Figures using real experimental measurements with the High Performance LDO of SLG51003 Power GreenPAK IC.

Figure 4: PSRR Measurement Bench Setup Diagram

Figure 5: Bode Analyser Suite Configuration

Figure 6: General Setup including the SLG51003 Power GreenPAK IC

The PSRR results are shown in Figure 7 and Table 3.

Figure 7: SLG51003 PSRR plot with selected capacitors for bench measurements

Analysing data obtained in Table 3indicates that the HP LDO of the SLG51003 retains a lower PSRR value with lower capacitance but still maintaining relevant performance. The higher capacitance provides significant performance improvement for PSRR results in the High Frequency range. Considerable impact on measurement results may affect effective capacitance after derating.

Figure 8: Derated measured capacitance with 2.85V DC voltage offset

Figure 8 shows the real measured capacitance with a 2.85V DC voltage offset applied. As can be seen, the real value is much lower than specified. Therefore, it is customary to use the concept of effective capacitance.

Constant Output Load variations and PSRR value

Another factor that impacts the PSRR performance is the value of the output load. Even if using a lower current in some cases can improve the PSRR performance, this value cannot be considered, given that most LDOs have been optimised to work within the typical recommendations of the output load.

Figure 9: PSRR plot constant load dependance on HP LDO with a 10µF C2012X5R1C106K085AC output capacitor

Analysing Table 4, SLG51003 shows better optimisation for a higher output load. This provides a significant benefit for powering in a system that requires high performance with high output current on the LDO and at the same time have acceptable high performance for lower load.

Conclusion

In applications requiring a high-performance low-dropout regulator, the choice of output capacitor can either enhance or diminish performance. The SLG51003V, a multi-output PMIC with multiple LDOs, offers high power supply rejection ratio (98.5 dB at 1kHz and 68 dB at 1MHz for LDO_HP) and low noise (16 μV LDO_HP) under specified operating conditions.

Measurement data includes cases outside standard datasheet specifications, showing that the SLG51003V maintains strong performance under low capacitance and gains further improvement with higher capacitance after derating. Primarily used as an advanced sensor power supply, the SLG51003V contributes to system performance, image quality, and reliability – important factors in competitive markets focused on precision. Additionally, it provides Power GreenPAK features, including high configurability, status reporting, programmable scenarios, sequencing, GPIOs, and I²C interface support.