Fully integrated RF Synthesiser for low power uses

In order to achieve high performance and flexibility in a low power solution, CML has implemented a dual-loop architecture with a highly-configurable reference path, consisting of a separate PLL and VCO, used to minimise close-in phase noise and mitigate integer and fractional boundary spurious.

Managing phase noise and spurious performance are fundamental to meeting international, including ETSI, radio standards such as EN 300 113 and EN 300 086, mandated for narrow-band systems. The CMX940 has a number of design innovation such as a near noiseless clock multiplier technology which will deliver the high performance needed to meet these stringent requirements.

The CMX940 is capable of generating RF signals over a continuous frequency range from 49MHz to 2040MHz, with dual single-ended RF outputs to support Rx and Tx sub-systems. Only an external loop filter and clock reference are needed to provide a compact and high quality local oscillator (LO) source.

Many synthesisers targeting these application areas are based on a PLL IC with a large number of discrete external parts to implement the voltage-controlled oscillator (VCO), which consumes valuable PCB real estate. CML aims to reduce component count / board area, eliminate VCO tolerancing issues and speed up time to market with a more integrated silicon approach.

At carrier frequency of 500MHz the typical phase noise is -124 dBc/Hz at 12.5kHz offset and spurious products are better than -75 dBc. The CMX940 operates from a 3.0 to 3.6V supply, with a current consumption of between 23 and 64mA depending on device configuration, making it an well suited choice for portable and battery powered applications.