Getting The Most From Your Buck

As many modern cell phone designs allow the battery to discharge very close to the highest supply voltages of some phone applications before triggering the under voltage lockout, efficient and accurate power conversion down to the 100% duty cycle mode is of significant consideration.



Switched step down converters work with two phases: ON phase, where the pass FET is ON; and OFF phase where the pass FET is OFF and the synchronous rectifier conducts the current. The so-called duty cycle is classically the ratio between the ON phase duration and the total conversion period.



One of the main decisions, which has to be taken during the OFF state is the entry into the PFM mode. If the inductor current is detected as reversing during the OFF state, the PWM regulation mode is no longer the most efficient regulation mode and the converter should go into PFM mode.



As the input voltage gets closer to the desired output voltage, the buck converter duty cycle naturally increases. If the regulating frequency stays constant, the synchronous rectifier period — or so called OFF time — becomes very small. The main problem encountered by IC designers developing a converter working at extremely high duty cycles is the reduced amount of time during which the converter is in the OFF state. This time might not be sufficient to process OFF time relevant signals, which are necessary for proper transition between PFM and PWM mode, and this creates hazardous converter behaviour, sometimes even preventing PFM mode entry (Figure 1).





Figure 1: Schematic of the current reversal comparator sensing the switch voltage and detecting when the voltage goes positive within the OFF phase. When the comparator trips, the device goes into PFM mode. Note that when the OFF time becomes too small, the circuit might not get enough time to respond because of its propagation delay.



A solution to this problem from Texas Instruments was to implement a minimum OFF time PWM regulation in their new 4MHz buck converter, the TPS6269X. This device runs at 4MHz, so that OFF time does not get smaller than a critical time identified as 50ns. When the input voltage reduces and the natural OFF time for a 4MHz frequency is predicted to be less than 50ns, the regulation frequency slows down to guarantee fixed 50ns OFF time operation, even at very high duty cycles.





Figure 2: Locus of the inductor current ripple versus duty cycle (d) for different PWM regulation methods



Using fixed OFF time mode of regulation presents the advantage of having a much flatter inductor current ripple characteristic against input voltage. Even if the regulating frequency goes down, the current change in the inductor during the OFF time being independent from Vin and the OFF time being constant, the inductor current ripple remains constant under this mode of operation. This presents some advantages for easy filtering and easy output voltage ripple estimation.



Hysteresis Between PWM And PFM



The TPS6269X uses a single pulse PFM mode of operation. When the PFM load increases the single PFM pulses tend to merge. When they merge, the system should switch to the PWM mode of operation. In the other direction, when the inductor current reverses during the OFF time of PWM operation, the system should go into PFM mode.





Figure 3: Inductor current profile during the PFM to PWM operation/transition. PFM ON time being designed longer than PWM ON time ensure hysteresis between the 2 modes



To ensure proper operation during the transition between PFM and PWM mode it is important that the converter exhibits hysteresis between entry in and exit out of the PWM mode. This hysteresis can only be guaranteed by ensuring the PFM ON time is always longer than the PWM ON time by a safe margin.



As the device is operating at 4MHz until its OFF time equals 50ns and in a fixed 50ns OFF time mode for input voltages below this threshold, the PFM ON time has to be designed to be automatically adaptive to these two distinct modes of operation (fixed frequency and fixed OFF time).



The 4MHz constant frequency operation gives a PWM ON time, with the following value:



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The 50ns minimum OFF time operation predicts a PWM ON time value expressed as:



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These two equations intercept for a given input voltage considering a given output voltage. The PFM on time to be chosen is always the longest of both.





Figure 4: Schematic of the two PFM ON time generators triggered by the main comparator detecting that Vout is too low



The TPS6269X implements two PFM ON time generators. They trigger a monostable, which turns on the pass FET each time the main comparator sees the output voltage falling below the reference voltage. Each of the two PFM ON time circuits responds according to one of the above equations and is used in one of the corresponding two modes. The outputs of the two circuits are simply fed into an OR gate which, by definition, always lets the longest ON time go through. Adding some 20% hysteresis to both circuits guarantees a non chaotic mode transition under every input to output condition, despite varying modes of regulation (fixed frequency and fixed OFF time). This design technique guarantees that the PFM ON time is always long enough in respect of the PWM ON time to allow proper transition between the two modes.



By looking at the efficiency graph (Figure 5), it can be seen that the device still goes into PFM mode under light load for very extreme duty cycle and that no dip in the curve is observed during the PFM to PWM transition, which indicates good operation.





Figure 5: TPS6269X measured efficiency in the two modes of operation. SIP module composed of TPS6269X inserted in the PCB, one inductor, and the input and output capacitors