Adapting To Serve

The general need for efficiency touches every aspect of commercial activity, where small gains in one area can lead to large advantages in another. Consequently, with the amount of energy produced globally increasing in response to general requirements, making even small improvements in how that energy is generated, transferred, transformed and consumed can have a widespread impact. 

For this reason, the benefits and subsequent adoption of digital control in power supply design is now equally widespread; the migration from analog to digital control is directly related to the greater control and resultant efficiency gains it offers. Now, those semiconductor manufacturers serving this market are moving the technology on, to offer even greater efficiency gains.

Meeting the Challenges
The introduction of digital control brought with it the need for control algorithms, but the advantage of a programmable solution offers the additional flexibility to improve on that algorithm without needing to modify the associated hardware. To address this opportunity semiconductor manufacturers created the digital signal controller; a combination of a standard microcontroller and digital signal processor, closely coupled to the architectural features needed to implement advanced digital signal control, such as Analog/Digital Converters and PWM controllers.

Together, these features combine to create a powerful and flexible control solution that can be applied to many applications where the distribution, conversion or application of power needs to be carefully controlled. This may include AC/DC and DC/DC power supplies, as well as end-applications such as lighting, solar inverters or uninterruptible power supplies. 

Recently, Microchip announced the 3rd gen of its flagship DSC; the dsPIC33EP GS family, which delivers higher performance in a number of architectural areas, enabling the implementation of more sophisticated algorithms and faster control loops. Together, these performance improvements could lead to measurable performance gains in power supplies across a number of application areas.

Increasing the performance of a digital control loop ultimately relies on two aspects; the speed with which the analog feedback can be converted to the digital domain, and the speed with which that feedback can be processed to provide new control parameters. This is where the digital and analog domains meet and so any solution that hopes to achieve high performance really needs to be not only fully integrated but developed specifically with this challenging use-case in mind. Furthermore, an emerging demand for the ability to make algorithm changes without incurring any down-time is presenting semiconductor manufacturers with new challenges. The architectural developments implemented in the GS family have been designed to meet these and future demands.

Architectural Improvements

The two main architectural improvements in the GS family are aimed at improving efficiency in ‘real world’ situations; that is, with widely varying load conditions. The ability of a controller to adapt to changes in load directly relates to the power supply’s overall efficiency, and is equally directly related to the processing core’s performance and the speed of the ADCs used to measure the power supply’s main parameters.

Techniques such as adaptive, non-linear and predictive algorithms have all been proven to improve efficiency and to achieve this using the GS family, the core now runs at a higher frequency, delivering 70MIPS (compared with 50MIPS for the Second Generation dsPIC33 family). Furthermore, the core now features three sets of registers; an addition of two working sets not present in previous devices. This allows for near instantaneous context switching, as it removes the need to store/load data to/from registers when switching. Each register set is assigned a specific interrupt priority level and this feature alone can accelerate compensators by up to 50%.

Working in conjunction with the faster core are five improved 12-bit ADCs; their performance has also increased, delivering vastly reduced latency (300 instead of 600ns). As well as supporting differential inputs, each converter has a dedicated results register and can work autonomously to compare conversion results against pre-stored thresholds to detect over-, under- out-of-range results without interrupting the CPU.

As an illustration, implementing a 3-Pole-3-Zero (3P3Z) Compensator using the dsPIC33FJ (2nd gen) family would require 57 cycles at 20.0ns per cycle (50MHz), which equals 1.140μS; the same function in the 3rd gen ‘GS’ family takes only 38 cycles at 14.3ns (70MHz), which equates to 543nS. This performance improvement can be attributed to the architectural changes delivering 33% performance improvement, while the higher clock frequency provides a 40% improvement; these figures combined equate to a 52% improvement in latency, making the new GS family more than twice as fast as the 2nd gen family.

Live Updates

Another significant feature of the ‘GS’ family is its ability to support a live update of the control algorithm without powering down. In fact, the switchover between algorithms can be achieved in less than the time required for a single ADC cycle, meaning the power supply need never be taken down when upgrading the control algorithm.

It also means that, for example, the control algorithm can be updated from a 2P2Z to a 3P3Z without interruption, delivering measurable efficiency gains while remaining live and in service. Microchip claims that no other DSC can do this, and is a feature that has already drawn the attention of Server companies, which have the infrastructure in place to support live updates of control algorithms.

It is achieved in part through the implementation of dual-Flash partitions, allowing the bootloader to update one partition while the control code continues to run from the other; the program execution moves from one partition to the other seamlessly between PWM updates. For example, Microchip claims that in a power supply with a switching frequency of 250kHz the PWM cycle would be 4.0μS and in the GS family the 3P3Z compensator calculations would take less than 0.6μS, leaving in excess of 3.4μS for any time-critical initialisation to take place.

Live updates can be categorised from simple to very complex; a simple update would be easily reversible, while a very complex update would require most/all variables — including those that are time-critical — to be initialised. In this scenario the processing overhead required by the switchover would still leave ample processing time for initialisation, according to Microchip.

Partitioning flexibility allows various configurations, largely unlimited by the hardware, while a specific instruction (BOOTSWP) allows partition switching on the fly (without reset). The live update feature is supported in the 64kB versions for the ‘GS’ family (two blocks of 32kB).

Digital control in power supply design continues to displace analog control due to its flexibility and performance benefits. Implementing an advanced Digital Signal Controller at the heart of a control system offers even greater benefits in terms of performance and flexibility. By implementing significant architectural enhancements coupled with the innovative dual-Flash facility for live updates, the dsPIC33EP GS family offers designers with a new yet familiar platform for implementing more advanced digital control.

Through this kind of innovation, power supply deigns can be both smaller and consume less power; it’s claimed that a 1/8th Brick DC/DC converter based on the GS family would consume 80% less power, delivering 4% savings in dissipated heat and 0.26% increased efficiency in a 100W module. In a world where any gain is an advantage, DSCs are evolving to provide just that.