Mixed signal methodology offers high automation

23rd April 2015

Fraunhofer

Barney Scott

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The Intelligent IP Mixed Signal Design Flow methodology developed by the Design Automation group at the Fraunhofer Institute for ICs IIS offers an unparalleled degree of automation, especially for the otherwise time-consuming, error-prone analogue portion of the design. Mixed-signal ICs are found in many of today's microelectronics, from safety-critical automotive applications to medical and aerospace systems.

Although the analogue circuitry usually accounts for no more than 20% of the chip surface, the low degree of automation leads to high development costs and risky designs, a problem that is exacerbated by the growing reliance on miniaturisation in semiconductor technologies.

In several development projects, design engineers at Fraunhofer IIS were able to demonstrate significant improvements in efficiency by using intelligent IP mixed signal design flows. During the design of a multiphysical SMART sensor ASIC for instance, they reduced development costs and time by 40%. The result was the creation of various ASICs for different requirements in a single development cycle.

Efficiency gains will eventually be realised even further through the automatic selection of the architecture during the system design. This innovative design flow was successfully used during the development of an industrial high-resolution ADC and an extremely fast image sensor.

Johann Hauer, Head of Mixed Signal ASIC Development, IIS, has nothing but praise for the methodology: “Although we have been striving for automated analogue design processes for years, this complete design flow finally delivers the expected benefits for our daily development activities. A 40% reduction in development time and extremely reliable designs means that we can finally offer first-time-right designs with much shorter development cycles. Another key factor is the very high acceptance level among our design engineers due to the intuitive approach.”

Customers who outsource the development of mixed signal ASICs and IPs to Fraunhofer IIS can reap the benefits of this design flow today. Customers who develop their own integrated circuits can adopt the design flow beginning in 2016.

The design flow currently supports established production technologies from various manufacturers, from 350 down to 28nm. Even now, researchers are driving the further development of future ultra-low-power 28nm technologies in several research projects with the aim of demonstrating their utility in microelectronic systems used in safety-critical automobile applications and aerospace cabin communications.