LVDS clock fanout buffers use 60% less power

The IDT 8P34S clock fanout buffers accept a clock or data signal input, and duplicate (fan out) that signal for the purpose of providing a high-quality clock or data signal to multiple devices within the system. Enabling higher board densities and lower energy and cooling costs, the devices enable designers to reduce power consumption without performance penalties thanks to the low 1.8V supply voltage.

Pin-to-pin compatible with higher-voltage versions, the 8P34S family supports up to 12 outputs and is offered in five variants: the 2 output 8P34S1102i, the 4 output 8P34S1204i, the 6 output 8P34S1106i, the 8 output 8P34S1208i and the 12 output 8P34S1212i. Featuring low additive RMS phase noise down to 39 femtoseconds and support for frequencies up to 1.2GHz, the clock fanout buffers are compatible with standard LVDS devices. This makes it easy to deploy with minimal board footprint.

“Power consumption and the resulting heat dissipation is a serious concern in any high-performance system. In the past, higher performance implied higher power, and attempts to lower power consumption typically required an undesired trade-off in performance. As the industry leader in timing, it’s our goal to enable customers to meet their power requirements without sacrificing performance. IDT’s latest fanout buffer family is a great example of this, and will be a popular clock distribution product for our 4G wireless infrastructure and high-speed networking customers,” comments Christian Kermarrec, Vice President and General Manager, Timing and Synchronization Division, IDT.