Clock generation devices feature phase frequency detectors
Analog Devices has announced the family of low jitter, high performance clock generation and distribution devices supporting JESD204B subclass 1 clocking applications up to 7.5GHz. These products are suitable for high speed data converter clocking applications, with a scalable architecture to provide thousands of synchronised low jitter clocks, each with a complementary SYSREF signal.
The LTC6952 is a high performance, ultra low jitter, JESD204B clock generation and distribution device. It includes a Phase Locked Loop (PLL) core, consisting of a reference divider, Phase-Frequency Detector (PFD) with a phase-lock indicator, ultralow noise charge pump and integer feedback divider.
The LTC6952’s eleven outputs can be configured as up to five JESD204B subclass 1 device clock/SYSREF pairs plus one general purpose output, or simply 11 general purpose clock outputs for non-JESD204B applications.
Each output has its own individually programmable frequency divider and output driver. All outputs can be synchronised and set to precise phase alignment using individual coarse half-cycle digital delays and fine analog time delays.
For applications requiring more than eleven total outputs, multiple LTC6952s can be connected using the EZSync or ParallelSync synchronisation protocols.
The LTC6953 is the clock distribution function of the LTC6952. The LTC6955 is an 11 output fanout buffer with a parallel interface that selects one of three states per output group: in-phase, 180° out of phase, or power-down. The LTC6955-1 is the same as the LTC6955-1 except one output has an integrated ÷2.
All devices are offered in a 52-lead, 7x8mm plastic QFN package. The device is rated for operation from -40°C to 125°C junction temperature. Unused outputs can be powered down when not in use. Samples and evaluation board of all products are available immediately. Production quantities of all products will be available by the end of June.
The LTC6952 and LTC6955-1 will be demonstrated at IMS 2018, booth 1725, on June 12-14 in Philadelphia. The demo will show a scalable architecture for thousands of outputs.