Sondrel completes a multi-billion transistor chip design at 5nm

Graham Curren, Sondrel’s CEO, said, “With every new process node, the density and number of transistors per area increases dramatically, along with the overall complexity of designing in each process. For example, only a few years ago, our biggest chip had 30 billion transistors. Our latest design delivered over 50 billion transistors. Many factors were considered to implement a 5nm design: number of engineers working on the design, the size of the design database, the complexity of data management, the number of design rules, and the expanded capability of compute infrastructure. Such a project also requires a sophisticated project management system to oversee every aspect of the design to ensure on-time delivery of the highest quality. We typically have several such mega chip designs on the go at the same time as, with more than 130 engineers, we have in house the skilled resources to create the teams needed for each stage of the design. And we are using all these skills for even more complex designs at 3nm with over a hundred billion transistors.”