Silicon Laboratories Expands Family Of High-Performance MCUs With Lower Cost Options

The T610 features byte-programmable EPROM that can be initially programmed while still leaving room for programming memory at a later time, making the T610’s EPROM more flexible than traditional one-time programmable memory. The T610 is based on a patented, pipelined, single-cycle 8051 core that delivers up to 25 MIPS of CPU bandwidth while providing high functional density per square millimeter with on-chip high-performance features such as a highly accurate ADC for analog measurement, voltage regulator and precision internal oscillator ultimately reducing the number of external components and reducing the size and cost of the end-product.

Silicon Laboratories’ small form factor MCUs provide “four-corner operation,” which means they do not require special operating conditions to achieve the optimal datasheet specifications. The CPU is designed to operate at 25MHz over the entire allowed operating temperature and power supply voltage ranges. ADC speed and accuracy is also guaranteed over the entire allowed temperature and voltage supply range with the CPU operating at full speed. The on-board precision oscillator is designed and calibrated to two percent for worst case temperature and supply voltage so the accuracy always meets the minimum specification.

Systems using the T610 family can be designed and prototyped using the F310 family Flash memory equivalent and then switched to T610 without any hardware changes. A full-featured development kit is available containing all the hardware and software required to develop an embedded system using the T610 including a socket to program EPROM memory.

“The C8051T610 product family adds to Silicon Laboratories’ portfolio of more than 70 high performance small form factor MCUs, giving customers the broadest range of options for their space-constrained applications,” said Derrell Coker, vice president of Silicon Laboratories. “Pin compatibility with our other popular devices allows engineers to migrate between different features and capabilities when upgrading performance or reducing system cost.”