Renesas Technology Develops Future 32-bit RX600 Series CISC MCUs, Based its Next-Generation ‘RX’ Architecture

The RX Family is being developed in response to the changing market needs for high-speed, high- performance, large capacity on-chip memory and power sensitive MCUs to support the growing complexity and performance demand of embedded systems. With the launch of the RX Family, Renesas aims to take advantage of the high growth 32-bit application space by providing a scalable CISC architecture. Renesas announced the development of a next-generation CISC CPU core architecture in May 2007. Completion of the design of the RX architecture was announced in November 2007.

“The RX Family is destined to become a mainstay of Renesas’ future MCU business,” said Yasushi Akao, board director and general manager, MCU business group, Renesas Technology Corp. “The new product line will comprise next-generation devices that complement and enhance the company’s existing 16-bit and 32-bit CISC MCUs. Besides the new 32-bit RX600 Series, the RX Family will also include the 16-bit RX200 Series, devices targeted at applications that need low power consumption and high speed.”

The devices will have up to 4MB on-chip flash, up to 256KB SRAM and highly integrated advanced peripheral functions. They will also be upward-compatible with Renesas’ current product lines, providing customers an easy upgrade path to higher performance devices.