Arm adds more safety in Cortex-M23 for automotive

To speed up time-to-market for automotive partners, Arm has added even more functional safety capabilities to M-profile cores and certified them with an external assessor for ISO 26262.

This elevates the safety starting position for chip designers, easing their safety efforts, and allowing them to focus on other areas.

With the release of the updated Cortex-M23, the full portfolio of Cortex-M processors, including Cortex-M85 and Cortex-M55 now include leading-edge functional safety features.

Within all vehicles, there are small, single functions that need cost-effective compute solutions. It is in this space that achieving functional safety within the constraints of low power and area is an ongoing challenge.

Cortex-M23 is Arm’s most power efficient Cortex-M CPU and has been updated to include functional safety features that elevate diagnostic coverage for safety critical applications. Examples include ultrasonic parking sensors for parking assistance, tire pressure and rain sensors, lighting and LED controllers for headlights and brake lights, to name a few. Many of these applications require ASIL B, a medium level of integrity, for which the updated Cortex-M23 could be the perfect fit with its single core safety mechanisms.

ASIL B level normally requires the detection of 90 per cent of single point faults, and that transient faults are addressed, if applicable.

Transient faults are tricky in that they can go easily undetected. This is because a particle could hit an area of the design and flip one bit of data, but it is not long before the next bit of data is written to that location, overwriting the flipped bit.

The updated Cortex-M23 adds transient fault protection to address this issue for applications that are constrained by area and cost where a dual-core lockstep approach would be undesirable.

It also adds interface protection for the detection of faults at the boundary of the CPU, removing more work at the system level for chip designers. The use of a Software Test Library for Cortex-M23 would also provide more diagnostic coverage of permanent faults, complementing the internal core safety mechanisms.

Moreover, these additional features have no impact on benchmark performance compared to the previous Cortex-M23, making adoption simpler.

For applications where dual-core lockstep is required, Arm has now delivered a new Dual Core Lockstep application note specific to Cortex-M23. This document gives guidance on how to implement this feature on Cortex-M23 and what to watch out for when implementing it. This might also be the right solution for an ASIL B application if a user’s design can support the additional die area and power that comes with a dual lockstep implementation.

Cortex-M23, which was first launched in 2016, implements the ARMv8-M architecture, bringing more instructions and system level features. Those experienced with Cortex-M0+ see many of the same energy-efficiency benefits in Cortex-M23. These benefits include deep-sleep modes and sleep-on-exit, which make it ideal for low-power applications. With more vehicles becoming electrified, Tier 1s must develop solutions that can meet the power needs of OEMs, for which Cortex-M processors are well suited.

Developers can design more robust and safer systems using the optional MPU (Memory Protection Unit). The MPU can be programmed to define regions of memory, assign certain attributes and access permissions depending on the task.

When an application attempts to access a region of memory for which it has not been authorised, the MPU can trigger a fault exception.